Patents Assigned to Cubic Wafer, Inc.
  • Publication number: 20080157787
    Abstract: A method of creating an improved sensitivity capacitive fingerprint sensor involves forming vias from a first side of a sensor chip having an array of capacitive sensors, making the vias electrically conductive, and attaching a cover plate over the first side of the sensor chip spaced from the sensor chip by a distance of less than 25 ?m. An improved sensitivity capacitive fingerprint sensor has a capacitive sensor array including multiple sensor cells and electrically conductive, through-chip vias extending from connection points for sensor cell circuitry to a back side of the capacitive sensor array, a chip including active detection circuitry and electrical connection points, the electrical connection points being respectively connected to corresponding ones of the sensor cell circuitry connection points, and a cover plate, disposed above the sensor cells at a spacing of less than 25 ?m.
    Type: Application
    Filed: January 3, 2007
    Publication date: July 3, 2008
    Applicant: CUBIC WAFER, INC.
    Inventors: Abhay Misra, John Trezza
  • Publication number: 20070281460
    Abstract: A method involves forming vias in a blank semiconductor wafer, making at least some of the vias in the blank semiconductor wafer electrically conductive, and performing front end processing on the blank wafer so as to create devices on the wafer that are connected to the electrically conductive vias.
    Type: Application
    Filed: December 29, 2006
    Publication date: December 6, 2007
    Applicant: CUBIC WAFER, INC.
    Inventor: John Trezza
  • Patent number: 7289547
    Abstract: A detector is disposed on the passive side of a laser to detect photon leakage through the passive side mirror and measure as current created in the detector via a Schottky contact.
    Type: Grant
    Filed: October 29, 2003
    Date of Patent: October 30, 2007
    Assignee: Cubic Wafer, Inc.
    Inventors: John Trezza, Mohamed Diagne
  • Publication number: 20070197013
    Abstract: An apparatus involves a semiconductor wafer that has been back-end processed, the semiconductor wafer including a substrate, electronic devices and multiple metalization layers, a via extending from an outer surface of the substrate through the substrate to a metalization layer from among the multiple metalization layers, and an electrically conductive material within the via, the electrically conductive material forming an electrically conductive path from the metalization layer to the outer surface. A method of processing a semiconductor wafer that has been front-end and back-end processed involves forming a via in the semiconductor wafer extending from a surface of the wafer, into and through semiconductor material, to a metalization layer formed during the back-end processing by etching the semiconductor wafer; and making the via electrically conductive so as to form an electrical path within the via extending from the surface of the wafer to the metalization layer.
    Type: Application
    Filed: November 6, 2006
    Publication date: August 23, 2007
    Applicant: CUBIC WAFER, INC.
    Inventor: JOHN TREZZA
  • Publication number: 20070138562
    Abstract: An integrated circuit chip includes devices formed by doping of a semiconductor on a substrate and at least one post-device formation through-chip via made up of an annulus of insulating material, an annulus of metallization bounding an outer surface of the annulus of insulating material and an annulus of electrically conductive material within the annulus of insulating material, the annulus of metallization and the annulus of electrically conductive material being electrically isolated from each another.
    Type: Application
    Filed: November 6, 2006
    Publication date: June 21, 2007
    Applicant: Cubic Wafer, Inc.
    Inventor: John Trezza
  • Patent number: 7215032
    Abstract: A method performed on a wafer having multiple chips, each including a doped semiconductor and substrate, involves etching an annulus trench partially into the substrate, metalizing an inner and outer perimeter side wall of the annulus trench with a metal, etching a via trench within the periphery of the annulus trench, making a length of the via trench electrically conductive, and thinning the substrate to expose the metal and the electrically conductive material so that the metal on the outer perimeter side wall and on the inner perimeter side wall are both electrically separated from each other and from the electrically conductive material.
    Type: Grant
    Filed: January 10, 2006
    Date of Patent: May 8, 2007
    Assignee: Cubic Wafer, Inc.
    Inventor: John Trezza
  • Patent number: 7157372
    Abstract: A method performed on a wafer having multiple chips, each including a doped semiconductor and substrate, involves etching an annulus trench partially into the substrate, metalizing the annulus trench with a metal, etching a via trench within the periphery of the annulus trench, making a length of the via trench electrically conductive, and thinning the substrate to expose the metal and the electrically conductive material.
    Type: Grant
    Filed: January 10, 2006
    Date of Patent: January 2, 2007
    Assignee: Cubic Wafer Inc.
    Inventor: John Trezza
  • Patent number: 7092424
    Abstract: A unit has an array of lasers having an emission surface through which beams can be emitted in a substantially vertical direction so as to define an emission side, drive electronics connected to a side opposite to the emission side of the array of lasers, and an array of modulators, located on the emission side of the array of lasers and connected to the drive electronics.
    Type: Grant
    Filed: September 30, 2003
    Date of Patent: August 15, 2006
    Assignee: Cubic Wafer, Inc.
    Inventor: John Trezza
  • Patent number: 7077577
    Abstract: An apparatus to accurately hold an optical fiber within a commercial fiber optic connector. The connector has a first high precision slice having multiple holes of a first area and a first alignment opening and a second high precision slice having multiple holes of a second area and a second alignment opening. The holes of the first high precision slice are arranged relative to the first alignment opening so that, when the second high precision slice and the first high precision slice are juxtaposed with one another and the first alignment opening and the second alignment opening are aligned, the holes of the first high precision slice and the holes of the second high precision slice will be offset relative to each other and will define an opening having an area less than a smaller of the first area and second area. The opening is capable of closely constraining an optical fiber inserted therethrough.
    Type: Grant
    Filed: June 27, 2003
    Date of Patent: July 18, 2006
    Assignee: Cubic Wafer, Inc.
    Inventors: John Trezza, Keith Kang, Greg Dudoff, Ronald Olson
  • Patent number: D543953
    Type: Grant
    Filed: September 2, 2003
    Date of Patent: June 5, 2007
    Assignee: Cubic Wafer, Inc.
    Inventors: Roger Dugas, Ross L. Frushour