Patents Assigned to Cufer Asset Ltd. L.L.C.
  • Patent number: 9584539
    Abstract: A method scans a second web page linked to a first web page being displayed by a browser. The method identifies a target link to the second web page. Prior to receiving a user selection of the target link, the method prefetches content from the second web page and loads it into a safe cache before receiving the user selection of the target link. The method scans the prefetched content for a security threat, within the safe cache, which is configured to prevent the prefetched content from altering a memory or storage location external to the safe cache. The method detects user placement of a cursor proximate to the target link and, in response to identifying a security threat, presents a warning to the user, or in response to identifying no threat or the user opting to ignore the warning, causing display of a second window comprising the prefetched content.
    Type: Grant
    Filed: February 19, 2016
    Date of Patent: February 28, 2017
    Assignee: Cufer Asset Ltd. L.L.C.
    Inventors: Scott Milener, Wendell Brown, James Kelly
  • Patent number: 9324629
    Abstract: A method for use with multiple chips, each respectively having a bonding surface including electrical contacts and a surface on a side opposite the bonding surface involves bringing a hardenable material located on a body into contact with the multiple chips, hardening the hardenable material so as to constrain at least a portion of each of the multiple chips, moving the multiple chips from a first location to a second location, applying a force to the body such that the hardened, hardenable material will uniformly transfer a vertical force, applied to the body, to the chips so as to bring, under pressure, a bonding surface of each individual chip into contact with a bonding surface of an element to which the individual chips will be bonded, at the second location, without causing damage to the individual chips, element, or bonding surface.
    Type: Grant
    Filed: March 30, 2007
    Date of Patent: April 26, 2016
    Assignee: CUFER ASSET LTD. L.L.C.
    Inventors: Roger Dugas, John Trezza
  • Patent number: 9299088
    Abstract: A multi-dimensional information repository storing data structures and tags associated with individual ones of the data structures. The data structures are tagged according to locations and defined regions relative to the surface of the Earth, and a data retrieval system retrieves information from the data structures according to location data accompanying requests for data. Data structures can also be tagged relative to time in addition to location and defined regions, and both tags can be used in retrieving data structures. A subscription server using the data repository can have a communication module for receiving data requests accompanied by location data and a code set for managing retrieval of information from the data repository. The subscription server can use the accompanying location data to determine a location in pre-defined regions, and use the pre-defined region information to retrieve information related to the pre-defined regions in response to the data requests.
    Type: Grant
    Filed: April 24, 2015
    Date of Patent: March 29, 2016
    Assignee: Cufer Asset Ltd. L.L.C.
    Inventor: Harry A. Glorikian
  • Patent number: 9270699
    Abstract: A method scans a second web page linked to a first web page being displayed by a browser in a browser window. The method identifies, in the first web page, a target link to the second web page. Prior to receiving a user selection of the target link, the method prefetches content from the second web page and loads it into a safe cache before receiving the user selection of the target link and before the content of the second web page is opened by an application configured to provide access to the content of the second web page. The method scans the prefetched content from the second web page for a security threat, within the safe cache, which is configured to prevent the prefetched content from altering a memory location or storage location external to the safe cache.
    Type: Grant
    Filed: July 11, 2014
    Date of Patent: February 23, 2016
    Assignee: Cufer Asset Ltd. L.L.C.
    Inventors: Scott Milener, Wendell Brown, James Kelly
  • Patent number: 9147635
    Abstract: An electrical connection between two chips includes an IC pad on a first chip, an IC pad on a second chip, a first barrier metal over the IC pad of the first chip, a second barrier metal over the IC pad of the second chip, a malleable electrically conductive metal, different from the barrier metals, trapped between the first barrier metal and the second barrier metal, the first barrier metal, the malleable conductive metal and the second barrier metal forming a complete electrically conductive path between the IC pad of the first chip and the IC pad of the second chip.
    Type: Grant
    Filed: December 13, 2010
    Date of Patent: September 29, 2015
    Assignee: CUFER ASSET LTD. L.L.C.
    Inventors: John Trezza, John Callahan, Gregory Dudoff
  • Patent number: 8846445
    Abstract: A system for connecting a first chip to a second chip having a post on the first chip having a first metallic material, a recessed wall within the second chip and defining a well within the second chip, a conductive diffusion layer material on a surface of the recessed wall within the well, and a malleable electrically conductive material on the post, the post being dimensioned for insertion into the well such that the malleable electrically conductive material will deform within the well and, upon heating to at least a tack temperature for the malleable, electrically conductive material, will form an electrically conductive tack connection with the diffusion layer to create an electrically conductive path between the first chip and the second chip.
    Type: Grant
    Filed: June 20, 2011
    Date of Patent: September 30, 2014
    Assignee: Cufer Asset Ltd. L.L.C.
    Inventor: John Trezza
  • Patent number: 8643186
    Abstract: An apparatus involves a semiconductor wafer that has been back-end processed, the semiconductor wafer including a substrate, electronic devices and multiple metalization layers, a via extending from an outer surface of the substrate through the substrate to a metalization layer from among the multiple metalization layers, and an electrically conductive material within the via, the electrically conductive material forming an electrically conductive path from the metalization layer to the outer surface. A method of processing a semiconductor wafer that has been front-end and back-end processed involves forming a via in the semiconductor wafer extending from a surface of the wafer, into and through semiconductor material, to a metalization layer formed during the back-end processing by etching the semiconductor wafer; and making the via electrically conductive so as to form an electrical path within the via extending from the surface of the wafer to the metalization layer.
    Type: Grant
    Filed: July 29, 2010
    Date of Patent: February 4, 2014
    Assignee: Cufer Asset Ltd. L.L.C.
    Inventor: John Trezza
  • Patent number: 8499434
    Abstract: A method of creating an improved sensitivity capacitive fingerprint sensor involves forming vias from a first side of a sensor chip having an array of capacitive sensors, making the vias electrically conductive, and attaching a cover plate over the first side of the sensor chip spaced from the sensor chip by a distance of less than 25 ?m. An improved sensitivity capacitive fingerprint sensor has a capacitive sensor array including multiple sensor cells and electrically conductive, through-chip vias extending from connection points for sensor cell circuitry to a back side of the capacitive sensor array, a chip including active detection circuitry and electrical connection points, the electrical connection points being respectively connected to corresponding ones of the sensor cell circuitry connection points, and a cover plate, disposed above the sensor cells at a spacing of less than 25 ?m.
    Type: Grant
    Filed: November 11, 2009
    Date of Patent: August 6, 2013
    Assignee: Cufer Asset Ltd. L.L.C.
    Inventors: Abhay Misra, John Trezza
  • Patent number: 8456015
    Abstract: A method performed on a wafer having multiple chips each including a doped semiconductor and substrate involves etching an annulus trench, metalizing an inner and an outer perimeter side wall of the annulus trench, etching a via trench into the wafer, making a length of the via trench electrically conductive, thinning a surface of the substrate.
    Type: Grant
    Filed: January 6, 2010
    Date of Patent: June 4, 2013
    Assignee: Cufer Asset Ltd. L.L.C.
    Inventor: John Trezza
  • Patent number: 8283778
    Abstract: A chip has a wafer portion of a first coefficient of thermal expansion, the wafer portion including at least one via defined by a peripheral sidewall, an insulating region having second average coefficient of thermal expansion, located within the via and covering at least a portion of the peripheral sidewall to a first thickness, a metallic region having a third average coefficient of thermal expansion, located within the via and covering the insulator to a second thickness, the first thickness and second thickness being selected such that expansion of the combination of the insulator and the metal due to heat will match the expansion of the wafer portion as a result of the combined effect of the first and second thicknesses and their respective second and third average coefficients of thermal expansion.
    Type: Grant
    Filed: February 16, 2007
    Date of Patent: October 9, 2012
    Assignee: Cufer Asset Ltd. L.L.C.
    Inventor: John Trezza
  • Patent number: 8232194
    Abstract: A method of creating a semiconductor chip having a substrate, a doped semiconductor material abutting the substrate and a device pad at an outer side of the doped semiconductor material involves creating a via through at least a portion of the substrate, the via having a periphery and a bottom at a location and depth sufficient to bring the via into proximity with the device pad but be physically spaced apart from the device pad, introducing an electrically conductive material into the via, and connecting the electrically conductive material to a signal source so the signal will deliberately be propagated from the electrically conductive material to the device pad without any direct electrical connection existing between the electrically conductive material and the device pad.
    Type: Grant
    Filed: October 14, 2011
    Date of Patent: July 31, 2012
    Assignee: Cufer Asset Ltd. L.L.C.
    Inventor: John Trezza
  • Patent number: 8197627
    Abstract: An apparatus for use with multiple chips having multiple posts as to engage at least a portion of a surface of one of the multiple chips, a frame configured to releasably constrain each of the posts so that, when unconstrained, each individual post can contact an individual chip and, when constrained, will allow a uniform vertical force to be applied to the chips.
    Type: Grant
    Filed: April 15, 2011
    Date of Patent: June 12, 2012
    Assignee: Cufer Asset Ltd. L.L.C.
    Inventors: John Trezza, Ross Frushour
  • Patent number: 8197626
    Abstract: An apparatus for use with multiple individual chips having a rigid plate, and a deformable membrane located on the plate, the deformable membrane having a thickness sufficient to allow the deformable membrane to peripherally conform to each of the individual multiple chips irrespective of any difference in height among the multiple individual chips and to prevent each of the multiple individual chips from moving in a lateral direction, the deformable membrane being configured to uniformly transfer a vertical force, applied to the rigid plate, to the chips so as to bring, under pressure, a bonding surface of each individual chip into contact with a bonding surface of an element to which the individual chips will be bonded during a connect and release cycle without causing damage to the individual chips or bonding surface.
    Type: Grant
    Filed: April 14, 2011
    Date of Patent: June 12, 2012
    Assignee: Cufer Asset Ltd. L.L.C.
    Inventors: John Trezza, Ross Frushour
  • Patent number: 8154131
    Abstract: A semiconductor chip, having IC pads, the semiconductor chip having a device, electrically connected to at least one electrical contact through the IC pad, the electrical contact having a height and a cross sectional profile, through the height, configured to facilitate penetration of at least a portion of the electrical contact into a malleable contact on a second semiconductor chip.
    Type: Grant
    Filed: January 10, 2006
    Date of Patent: April 10, 2012
    Assignee: Cufer Asset Ltd. L.L.C.
    Inventors: John Trezza, John Callahan, Gregory Dudoff
  • Patent number: 8093729
    Abstract: An electrically conductive interconnect system has a post, extending above a supporting surface, the post including a rigid material, a coating on the rigid material, wherein the post and has a first width at the supporting surface and a second width at a distance removed from the supporting surface, and the post narrows from the first width to the second width. A method of electrically connecting a portion of a first supporting surface to a portion of a second supporting surface involves bringing a post on the first supporting surface into contact with an electrically conductive material located on the second supporting surface, softening the electrically conductive material, causing a separation distance between the first supporting surface and the second supporting distance to decrease so that a portion of the post will be surrounded by the electrically conductive material, and allowing the temperature of the electrically conductive material to decrease.
    Type: Grant
    Filed: July 16, 2007
    Date of Patent: January 10, 2012
    Assignee: Cufer Asset Ltd. L.L.C.
    Inventor: John Trezza
  • Patent number: 8084851
    Abstract: A module has at least two ICs connected to each other such that they lie in different planes and are arranged as a first stack of ICs, a third IC is connected to at least one of the at least two ICs, wherein the third IC is off plane from both of the at least two ICs.
    Type: Grant
    Filed: February 23, 2010
    Date of Patent: December 27, 2011
    Assignee: Cufer Asset Ltd. L.L.C.
    Inventor: John Trezza
  • Patent number: 8067312
    Abstract: An integrated circuit chip includes devices formed by doping of a semiconductor on a substrate and at least one post-device formation through-chip via made up of an annulus of insulating material, an annulus of metallization bounding an outer surface of the annulus of insulating material and an annulus of electrically conductive material within the annulus of insulating material, the annulus of metallization and the annulus of electrically conductive material being electrically isolated from each another.
    Type: Grant
    Filed: April 16, 2010
    Date of Patent: November 29, 2011
    Assignee: Cufer Asset Ltd. L.L.C.
    Inventor: John Trezza
  • Patent number: 8053903
    Abstract: A method of creating a semiconductor chip having a substrate, a doped semiconductor material abutting the substrate and a device pad at an outer side of the doped semiconductor material involves creating a via through at least a portion of the substrate, the via having a periphery and a bottom at a location and depth sufficient to bring the via into proximity with the device pad but be physically spaced apart from the device pad, introducing an electrically conductive material into the via, and connecting the electrically conductive material to a signal source so the signal will deliberately be propagated from the electrically conductive material to the device pad without any direct electrical connection existing between the electrically conductive material and the device pad.
    Type: Grant
    Filed: February 24, 2010
    Date of Patent: November 8, 2011
    Assignee: Cufer Asset Ltd. L.L.C.
    Inventor: John Trezza
  • Patent number: 8021922
    Abstract: A method of attaching a pair of chips, each having primary contacts that can be mated to each other, involves forming one or more secondary contacts on each of the two chips of a shape sufficient to prevent an initial attachment material from contacting any of the primary contacts during a preliminary attachment operation, the secondary contacts further having a height that will prevent the primary contacts from touching when the secondary contacts are brought into contact with each other, bringing the secondary contacts into closer and closer aligned proximity to each other at least until the primary contacts touch in a first phase, and heating the primary contacts until material between each of corresponding primary contacts on each of the chips in the pair forms an electrical connection.
    Type: Grant
    Filed: June 25, 2010
    Date of Patent: September 20, 2011
    Assignee: Cufer Asset Ltd. L.L.C.
    Inventor: John Trezza
  • Patent number: 7969192
    Abstract: A driver circuit includes a set of selectable drivers each having an individual drive capability, the drivers being selectable such that i) when a subset of the drivers is selected, a signal will be driven by the drivers at a first drive level, and ii) when the subset of the drivers and at least one additional driver is selected, signal will be driven by the drivers at a level that is greater than the first level by a level of drive provided by the least one additional driver.
    Type: Grant
    Filed: March 26, 2010
    Date of Patent: June 28, 2011
    Assignee: Cufer Asset Ltd. L.L.C.
    Inventors: Theodore J. Wyman, John Trezza