Patents Assigned to Cufer Asset Ltd. L.L.C.
  • Patent number: 7969015
    Abstract: A system for connecting a first chip to a second chip having a post on the first chip having a first metallic material, a recessed wall within the second chip and defining a well within the second chip, a conductive diffusion layer material on a surface of the recessed wall within the well, and a malleable electrically conductive material on the post, the post being dimensioned for insertion into the well such that the malleable electrically conductive material will deform within the well and, upon heating to at least a tack temperature for the malleable, electrically conductive material, will form an electrically conductive tack connection with the diffusion layer to create an electrically conductive path between the first chip and the second chip.
    Type: Grant
    Filed: January 10, 2006
    Date of Patent: June 28, 2011
    Assignee: Cufer Asset Ltd. L.L.C.
    Inventor: John Trezza
  • Patent number: 7960210
    Abstract: A packaging method involves attaching a first chip to a stable base, forming contact pads at locations on the stable base, applying a medium onto the stable base such that it electrically insulates sides of the first chip, forming electrical paths on the medium, attaching a second chip to the first chip to form an assembly, and removing the stable base. A package has at least two chips electrically connected to each other, at least one contact pad, an electrically conductive path extending from the contact pad to a contact point on at least one of the chips, a planarizing medium, and a coating material on top of the planarizing medium.
    Type: Grant
    Filed: April 23, 2007
    Date of Patent: June 14, 2011
    Assignee: Cufer Asset Ltd. L.L.C.
    Inventor: John Trezza
  • Patent number: 7946331
    Abstract: An apparatus for use with multiple chips having multiple posts as to engage at least a portion of a surface of one of the multiple chips, a frame configured to releasably constrain each of the posts so that, when unconstrained, each individual post can contact an individual chip and, when constrained, will allow a uniform vertical force to be applied to the chips.
    Type: Grant
    Filed: January 10, 2006
    Date of Patent: May 24, 2011
    Assignee: Cufer Asset Ltd. L.L.C.
    Inventors: John Trezza, Ross Frushour
  • Patent number: 7942182
    Abstract: An apparatus for use with multiple individual chips having a rigid plate, and a deformable membrane located on the plate, the deformable membrane having a thickness sufficient to allow the deformable membrane to peripherally conform to each of the individual multiple chips irrespective of any difference in height among the multiple individual chips and to prevent each of the multiple individual chips from moving in a lateral direction, the deformable membrane being configured to uniformly transfer a vertical force, applied to the rigid plate, to the chips so as to bring, under pressure, a bonding surface of each individual chip into contact with a bonding surface of an element to which the individual chips will be bonded during a connect and release cycle without causing damage to the individual chips or bonding surface.
    Type: Grant
    Filed: January 10, 2006
    Date of Patent: May 17, 2011
    Assignee: Cufer Asset Ltd. L.L.C.
    Inventors: John Trezza, Ross Frushour
  • Patent number: 7932584
    Abstract: A system has multiple discrete functional system subcomponents which, when interconnected form the system, each of the subcomponents being on a discrete substrate and being electrically interconnected to at least one of the other subcomponents by a through-chip via. A method of creating a system involves creating multiple discrete chips, each including at least one system subcomponent, forming electrically conductive vias in at least some of the chips such that some of the chips can be electrically connected to others of the chips, arranging the chips such that: some are coplanar in a first plane, at least one other lies in a second plane parallel to those in the first plane, and at least one of the chips in the first plane is connected to at least one of the chips in the second plane; and electrically interconnecting corresponding chips of the multiple discrete chips using the vias.
    Type: Grant
    Filed: February 16, 2007
    Date of Patent: April 26, 2011
    Assignee: Cufer Asset Ltd. L.L.C.
    Inventor: John Trezza
  • Patent number: 7919870
    Abstract: An integrated circuit chip includes devices formed by doping of a semiconductor on a substrate and at least one post-device formation through-chip via made up of an annulus of insulating material, an annulus of metallization bounding an outer surface of the annulus of insulating material and an annulus of electrically conductive material within the annulus of insulating material, the annulus of metallization and the annulus of electrically conductive material being electrically isolated from each another.
    Type: Grant
    Filed: November 6, 2006
    Date of Patent: April 5, 2011
    Assignee: Cufer Asset Ltd. L.L.C.
    Inventor: John Trezza
  • Patent number: 7884483
    Abstract: A method of electrically joining a first contact on a first wafer with a second contact on a second wafer, the first contact, a rigid material, and the second contact, a material that is malleable relative to the rigid material, such that when brought together the rigid material will penetrate the malleable material, the rigid and malleable materials both being electrically conductive involves bringing the rigid material into contact with the malleable material, applying a force to one of the first contact or the second contact so as to cause the rigid material to penetrate the malleable material, heating the rigid and malleable material so as to cause the malleable material to soften, and constraining the malleable material to within a pre-specified area.
    Type: Grant
    Filed: January 10, 2006
    Date of Patent: February 8, 2011
    Assignee: Cufer Asset Ltd. L.L.C.
    Inventors: John Trezza, John Callahan, Gregory Dudoff
  • Patent number: 7871927
    Abstract: A method of electrically conductive via formation in a fully processed wafer involves defining at least one trench area on a backside of the fully processed wafer, forming at least one trench within the trench area to an overall depth that will allow for a via formed within the trench to be seeded over its full length, forming the via within the trench into the fully processed wafer to a predetermined depth, depositing a seed layer over the full length of the via, and plating the seed layer to fill the via with an electrically conductive metal.
    Type: Grant
    Filed: October 15, 2007
    Date of Patent: January 18, 2011
    Assignee: Cufer Asset Ltd. L.L.C.
    Inventor: John Trezza