Abstract: Embodiments of the present disclosure provide a chopper amplifier circuit that includes an operational amplifier, and a notch filter to be operated by a chopping pulse. The notch filter has a first branch that has a first capacitor, and a second branch that has a second capacitor. A chopping delay switch is connected to the first branch and the second branch of the notch filter. A control circuit is to close the chopping delay switch to short-circuit the first branch and the second branch of the notch filter to each other. The control circuit is to detect establishment of feedback signal at the chopper amplifier. The control circuit is to open the chopping delay switch, responsive to detecting establishment of the feedback signal at the chopper amplifier.

Abstract: Apparatuses and methods of quadrature modulation and compensation are described. One touch controller includes a receiver sensing channel to measure a sense signal and generate at least four samples per one period of the sense signal. The touch controller includes quadrature demodulation logic to determine phase information of the sense signal using the at least four samples per one period of the sense signal and processing logic to execute a compensation algorithm to compensate for a phase mismatch of the touch controller based on the phase information.

Abstract: In an example embodiment, a method comprising identifying, by a primary-side controlled Universal Serial Bus Power Delivery (USB-PD) alternating current to direct current (AC-DC) converter, a first pulse, wherein the first pulse is received from a pulse transformer. The method further includes determining that a threshold duration of time is satisfied. In response to determining that the threshold duration of time is satisfied, the method includes identifying a second pulse, wherein the second pulse is received from the pulse transformer. The first pulse and the second pulse are used for control of a high-side field effect transistor (FET) and a low-side FET, where the high-side FET is coupled to an active clamp flyback (ACF) circuit and the low-side FET is coupled to a flyback transformer of the USB-PD AC-DC converter. In response to identifying the second pulse, the method further includes controlling operation of the high-side FET or the low-side FET.

Abstract: A controller includes a buck gate driver coupled to first high-side switch and first low-side switch of a buck-boost (BB) converter. A zero crossing detection (ZCD) comparator is coupled to first low-side switch. The ZCD comparator is to, while the BB converter operates in buck mode: detect zero current flow through inductor; and turn off first low-side switch in response to detecting the zero current. A boost gate driver is coupled to second high-side switch and second low-side switch of the BB converter. A reverse current detection (RCD) comparator coupled to second high-side switch. The RCD comparator is to, while the BB converter operates in boost mode: detect zero current flow through second high-side switch; and turn off second high-side switch in response to detecting the zero current.

Abstract: A method comprising controlling operation, by a secondary-side controlled Universal Serial Bus Power Delivery (USB-PD) alternating current to direct current (AC-DC) converter, a low-side field-effect transistor (FET). In response to controlling operation of the low-side FET, the method further includes triggering a zero-cross detection circuit. The method further includes measuring a first period of time between controlling operation of the low-side FET and triggering the zero-cross detection circuit. The method further includes measuring a second period of time between controlling operation of a high-side FET and triggering the zero-cross detection circuit. The method further includes adjusting a third period of time based on the first period of time and the second period of time, wherein the third period of time corresponds to a dead time between controlling operation of the high-side FET and the low-side FET.

Abstract: Disclosed are techniques for using a sense amplifier for the voltage path having an adjustable gain and a current amplifier for the current path having an adjustable sample-hold interval for demodulation of in-band ASK data in power transmitting devices of a wireless charging system. The sample-hold interval may be adjusted as a function of the error rate of the demodulated data and used to sample the modulated current when the adjustable gain of the voltage path is not able to track the modulated voltage. The adjustable sample-hold may function as a variable reference of a comparator used to compare the sampled current to generate the sensed current. A controller may flexibly adjust the gain, adjust the sample-hold interval, and/or select the sensed voltage or the sensed current path for further filtering, demodulation, decoding, and processing depending on the error rate under various loading, coupling scenarios, and phases of power transfer.

Abstract: A device includes a receiver to receive a packet over a channel at a first frequency and generate a sampled stream of data at a first sample rate corresponding to the first frequency. A data resampler circuit includes a re-timer engine to determine, using a fractional rate between the first sample rate and a crystal oscillator (XO)-divided sample rate, re-timer values including a difference between pulses of a pseudo clock corresponding to the XO-integer-divided sample rate and closest corresponding pulses of a clock corresponding to the first sample rate. The data resampler circuit includes a time shifting circuit to re-sample data values of the sampled stream of data associated with locations of the plurality of re-timer values. A correlation circuit uses the re-sampled data values, pseudo clock, and the re-timer values to match an expected data pattern to a corresponding data pattern detected in a frame delimiter of the packet.

Abstract: A method can include, by operation of first communication circuits, determining a quality of a plurality of communication frequencies according to wireless communications of a first protocol type; recording a quality of the communication frequencies; selecting communication frequencies for use by second communication circuits based on the quality of the communication frequencies; and wirelessly transmitting and receiving data with the second communication circuits according to a second protocol different than the first protocol; wherein the first and second communication circuits are collocated on the same device. Related devices and systems are also disclosed.

Abstract: A signature graph method is proposed to authenticate shared high-entropy data using a graph that can be easily identified by human eyes (or by computer image recognition algorithms). An example method for authenticating a shared data element comprises receiving a data element to be shared; transforming the data element to be shared into signature graph data, using at least one collision-resistant one-way mapping function; and rendering a human-perceptible representation of the signature graph data, such as an audible and/or visual representation, for perception by a human user. In some embodiments, transforming the data element comprises applying a cryptographic hash function to the data element, to obtain a first hash output, and applying a cryptographic hash function to the first hash output, to obtain the signature graph data.

Abstract: The embodiments described herein are directed at techniques to sharing a transmission medium in a Bluetooth transceiver/WLAN transceiver combination device. A first device may receive a request from a second device to use the wireless transmission medium. The second device may also transmit timing data to the first device. The first device may determine a period of time to allow the second device to use the wireless transmission medium based on the timing data.

Abstract: A method can include an integrated circuit device, determining if first communication circuits are operating in a first mode that wirelessly receives data at a first rate or a second mode that wirelessly receives data at a second rate that is lower than the first rate. If the first communication circuits are operating in the second mode, transmitting signals with the second communication circuits at a first power level, and if operating in the first mode, transmitting signals with the second communication circuits at a second power level that is lower than the first power level. In the first mode, X symbols per data bit are received and in the second mode, Y symbols per data bit are received, where X<Y. Corresponding devices and methods are also disclosed.

Abstract: A clock signal conversion circuit includes an amplification circuit configured to amplify a differential clock signal having sub rail-to-rail voltage swings relative to a supply voltage, such that an amplified differential clock signal output by the amplification circuit has complementary positive and negative signal components with full rail-to-rail voltage swings relative to the supply voltage.

Abstract: A Universal Serial Bus (USB)-Power Delivery (PD) integrated circuit (IC) controller is described. The controller includes: a driver circuit configured to control operation of a buck-boost converter electrically coupled to a USB voltage bus power line; a gate driver controller configured to control the driver circuit in a first mode, wherein changes in duty cycle are limited to a predetermined number of cycles in the first mode; a sense circuit configured to generate a sense signal proportional to current flowing in the USB voltage bus power line; and an analog detection circuit configured to detect whether a slew rate of the sense signal exceeds a reference slew rate. The gate driver controller is configured to override the limit placed on the changes in duty cycle in the first mode responsive to the analog detection circuit indicating that the slew rate of the sense signal exceeds the reference slew rate.

Abstract: Implementations disclosed describe techniques to optimize performance of wireless networks having multi-band connectivity by steering devices connecting to the network to preferred frequency ranges. In an example embodiment, a method may comprise receiving, a first probe request from a client device at a first access point of the wireless network, establishing a first association between the first access point and the client device, the first access point operating at a first frequency range of the wireless network, receiving a second probe request from the client device at a second access point, the second access point operating at a second frequency range of the wireless network, sending a transition request over the first access point to instruct the client device to transition to the second access point, and establishing a second association between the second access point and the client device.

Abstract: A device includes a receiver to receive a packet over a channel at a first frequency and generate a sampled stream of data at a first sample rate corresponding to the first frequency. A data resampler circuit includes a re-timer engine to determine, using a fractional rate between the first sample rate and a crystal oscillator (XO)-divided sample rate, re-timer values including a difference between pulses of a pseudo clock corresponding to the XO-integer-divided sample rate and closest corresponding pulses of a clock corresponding to the first sample rate. The data resampler circuit includes a time shifting circuit to re-sample data values of the sampled stream of data associated with locations of the plurality of re-timer values. A correlation circuit uses the re-sampled data values, pseudo clock, and the re-timer values to match an expected data pattern to a corresponding data pattern detected in a frame delimiter of the packet.

Abstract: A scanning operation is performed to measure a first capacitance of a first sensor arrangement located proximate a capacitive sensor that corresponds to a function of a device. In response to the first capacitance not exceeding a first threshold, the scanning operation measures a second capacitance of the capacitive sensor to create an output used to control the function of the device. In response to the first capacitance exceeding the first threshold, operation of the scanning operation is modified to skip measuring of the second capacitance or to refrain from transmitting the output to a host of the device for controlling the function.

Abstract: Systems, methods, and devices enhance integration of components of a wireless environment. Methods include determining, using a processing device, a plurality of contextual parameters identifying a plurality of settings associated with an application executed on a central wireless device and a plurality of wireless devices included in an operational environment of the central wireless device. Methods also include determining, using the processing device, a plurality of wireless device parameters and wireless connection parameters for the plurality of wireless devices based on the contextual parameters. Methods further include generating, using the processing device, instructions for each of the plurality of wireless devices based, at least in part, on the plurality of contextual parameters and a native format and wireless protocol of each of the plurality of wireless devices.

Abstract: A method can include in a first phase of a sensing operation, controlling at least a first switch to energize a sensor inductance; in a second phase of the sensing operation that follows the first phase, controlling at least a second switch to couple the sensor inductance to a first modulator capacitance to induce a first fly-back current from the sensor inductance, the first fly-back current generating a first modulator voltage at the first modulator capacitance, and in response to the first modulator voltage, controlling at least a third switch to generate a balance current that flows in an opposite direction to the fly-back current at the first modulator node. The first and second phases can be repeated to generate a first modulator voltage at the first modulator capacitance. the modulator voltage can be converted into a digital value representing the sensor inductance. Related devices and systems are also disclosed.

Abstract: An electrostatic discharge protection circuit capable of clamping both positive and negative ESD events and passing signals is provided. Generally, the circuit includes a p-channel field-effect transistor (PFET) clamp coupled to a pin to be protected, the PFET clamp including a plurality of PFETs in a DN-well, an n-channel field-effect transistors (NFET) clamp coupled between ground and the pin through the PFET clamp, the NFET clamp including a plurality of NFETs coupled in series, and a bias network for biasing a voltage of the DN well to substantially equal a voltage on the pin when the voltage on the pin is greater than ground potential, and to ground potential when the pin voltage is less than ground potential. The plurality of are PFETs coupled in parallel between the pin and the NFET clamp, each of the PFETs is coupled to the pin though one of a plurality ballast resistors.

Abstract: A secondary side controller for a flyback converter includes an integrated circuit (IC), which in turn includes: a synchronous rectifier (SR) sense pin coupled to a drain of an SR transistor on a secondary side of the flyback converter; a capacitor having a first side coupled to the SR sense pin, the capacitor to charge or discharge responsive to a voltage sensed at the SR sense pin; a diode-connected transistor coupled between a second side of the capacitor and ground; a first current mirror coupled to the diode-connected transistor and configured to receive, as input current, a reference current from a variable current source; and a peak detect transistor coupled to the diode-connected transistor and to an output of the first current mirror. The peak detect transistor is to output a peak detection signal in response to detecting current from the capacitor drop below the reference current.