Patents Assigned to CYPRESS SEMICONDUCTOR CORPORATIONS
  • Patent number: 11868561
    Abstract: Apparatuses and methods of multi-phase scanning of a touch panel are described. One apparatus selects a sequence having a number of one values, negative one values, and zero values. The one values correspond to an in-phase drive signal, the negative one values correspond to an opposite-phase drive signal, and the zero values correspond to a reference signal (e.g., reference voltage or ground). A sum of the sequence is equal to zero. The apparatus applies one of the in-phase drive signal, the opposite-phase drive signal, or the reference signal to each of a first set of electrodes at a first stage according to the sequence. The apparatus rotates the sequence to obtain a rotated sequence and applies one of the signals according to the rotated sequence. The apparatus receives sense signals to detect a presence of an object on the touch panel.
    Type: Grant
    Filed: May 26, 2021
    Date of Patent: January 9, 2024
    Assignee: Cypress Semiconductor Corporation
    Inventors: Volodymyr Bihday, Andriy Maharyta, Igor Kravets, Mykhaylo Krekhovetskyy, Ihor Musijchuk
  • Patent number: 11868565
    Abstract: Systems, methods, and devices improve the sensitivity of capacitive sensors. Devices may include an attenuator configured to receive an input from at least one sense electrode of a capacitive sensing device. The attenuator may be included in a sensing channel of a capacitive sensor. Devices may further include a signal generator coupled to an input of the attenuator. The signal generator may include one or more processors configured to generate a sinusoidal signal based, at least in part, on one or more noise characteristics of a scan sequence associated with one or more transmit electrodes of the capacitive sensing device, and provide the sinusoidal signal to the input of the attenuator.
    Type: Grant
    Filed: April 15, 2022
    Date of Patent: January 9, 2024
    Assignee: Cypress Semiconductor Corporation
    Inventors: Viktor Kremin, Oleksandr Pirogov, Vadym Grygorenko, Jens Weber
  • Patent number: 11869616
    Abstract: A system and method for centrally logging and aggregating miscompares on chip during a memory test. The method includes performing, by a built-in self-test (BIST) unit of a memory device, a memory test on one or more memory banks of the memory device using a first algorithm. The method includes generating miscompare results responsive to performing the memory test on the one or more memory banks of the memory device. The method includes determining failure diagnostic information based on the miscompare results. The method includes generating an error packet comprising the failure diagnostic information and the miscompare results. The method includes placing the error packet in a queue of a plurality of error packets to generate a queued error packet.
    Type: Grant
    Filed: November 11, 2021
    Date of Patent: January 9, 2024
    Assignee: Cypress Semiconductor Corporation
    Inventors: Senwen Kan, Andrew Payne, Jeffrey W Gossett, Michael Joseph Pluhta, Richard A Rodell, Jr., Bjarni Benjaminsson
  • Publication number: 20240008066
    Abstract: Systems, methods, and devices implement enhanced coexistence of radios within wireless devices. Methods include receiving a data packet at a wireless device, the data packet having a packet structure, the wireless device comprising a first wireless radio collocated with a second wireless radio, and identifying one or more features of the data packet based, at least in part, on the packet structure of the data packet. Methods further include updating a medium access grant signal associated with the second wireless radio based, at least in part, on the one or more features of the data packet, the medium access grant signal determining which of the first or second wireless radios has access to a communications medium.
    Type: Application
    Filed: June 30, 2022
    Publication date: January 4, 2024
    Applicant: Cypress Semiconductor Corporation
    Inventors: Munukutla Sandeep Sarma, Raghavendra Kencharla
  • Publication number: 20240007113
    Abstract: A time-to-digital converter (TDC) circuit includes phase error calculation circuitry to: determine phase error values based on a time difference between a input reference clock and a feedback clock of a digital phase-locked loop (DPLL) circuit, the input reference clock and the feedback clock being unsynchronized; and provide the phase error values to a digital loop filter (DLF) of the DPLL circuit. The TDC circuit further includes clock generation circuitry to: generate a filter clock that asserts a clock pulse in response to detecting each last-received pulse of the input reference clock and the feedback clock; and provide the filter clock to the DLF concurrently with providing the phase error values to the DLF that are synchronized to the filter clock.
    Type: Application
    Filed: June 12, 2023
    Publication date: January 4, 2024
    Applicant: Cypress Semiconductor Corporation
    Inventor: Avri Harush
  • Publication number: 20240008279
    Abstract: A semiconductor device and method of fabricating the same are disclosed. The method includes depositing a polysilicon gate layer over a gate dielectric formed over a surface of a substrate in a peripheral region, forming a dielectric layer over the polysilicon gate layer and depositing a height-enhancing (HE) film over the dielectric layer. The HE film, the dielectric layer, the polysilicon gate layer and the gate dielectric are then patterned for a high-voltage Field Effect Transistor (HVFET) gate to be formed in the peripheral region. A high energy implant is performed to form at least one lightly doped region in a source or drain region in the substrate adjacent to the HVFET gate. The HE film is then removed, and a low voltage (LV) logic FET formed on the substrate in the peripheral region. In one embodiment, the LV logic FET is a high-k metal-gate logic FET.
    Type: Application
    Filed: June 26, 2023
    Publication date: January 4, 2024
    Applicant: Cypress Semiconductor Corporation
    Inventors: Chun Chen, James Pak, Unsoon KIM, Inkuk Kang, Sung-Taeg Kang, Kuo Tung Chang
  • Patent number: 11862959
    Abstract: A system includes a first USB Type-C Power Delivery (USB-C/PD) port and a control circuit operatively coupled to the first USB-C/PD port. The control circuit is configured to determine whether a short circuit condition has occurred based on a first threshold voltage. The control circuit is also configured to turn off a ground isolation switch when short circuit condition occurs. The control circuit is further configured to determine a whether a voltage on a ground line is less than a second threshold voltage. The control circuit is further configured to turn on the ground isolation switch when the voltage on the ground line is less than the second threshold voltage. The control circuit may perform one or more error recovery operations after turning on the ground isolation switch.
    Type: Grant
    Filed: April 26, 2022
    Date of Patent: January 2, 2024
    Assignee: Cypress Semiconductor Corporation
    Inventors: Arun Khamesra, Hariom Rai, Pulkit Shah
  • Patent number: 11864089
    Abstract: Implementations disclosed describe systems and methods that include establishing, by a wireless device, a communication link with a wireless access point (AP) device over an operating channel, the wireless AP device providing a single-band access within a first frequency band; time-multiplexing, by the wireless device, transmitting beacons or probes within a second frequency band with communicating with the wireless AP device over the operating channel within the first frequency band; and configuring the beacons or probes to advertise, to other wireless devices in the second frequency band, availability of connection to the wireless AP device over the operating channel within the first frequency band.
    Type: Grant
    Filed: December 2, 2021
    Date of Patent: January 2, 2024
    Assignee: Cypress Semiconductor Corporation
    Inventors: Vivek R. Vellore, Prashant Kota
  • Patent number: 11853498
    Abstract: Apparatuses and methods of shielding for capacitance-to-digital code conversion are described. One apparatus includes a capacitance-to-digital converter (CDC) for measuring a self-capacitance of a sensor electrode. The capacitance-to-digital code converter can in a first phase, apply a supply voltage to the sensor electrode. The sensor electrode and a shield electrode, the form a mutual capacitance with the sensor electrode. The CDC, in a second phase, couples the shield electrode to a ground potential and the sensor electrode to a first modulation capacitor. The first modulation capacitor is pre-charged to a reference voltage. The CDC, in a third phase, couples the sensor electrode and the shield electrode to the ground potential. The CDC, in a fourth phase, couples the shield electrode to the ground potential and the sensor electrode to a second modulation capacitor. The second modulation capacitor is pre-charged to the reference voltage.
    Type: Grant
    Filed: December 16, 2022
    Date of Patent: December 26, 2023
    Assignee: Cypress Semiconductor Corporation
    Inventors: Mark Healy, Daniel O'Keeffe
  • Publication number: 20230402914
    Abstract: Controlling power factor correction (PFC) in a secondary-controlled alternating current (AC) to direct current (DC) (AC-DC) power adapter is described. In one embodiment, an apparatus includes a transformer, a primary-side controller coupled to the transformer, a PFC component coupled to the primary-side controller, and a secondary-side controller coupled to the transformer. The secondary-side controller is configured at least to obtain data informative of an amount of power, and control, based on the amount of power, a PFC operating mode of the PFC component.
    Type: Application
    Filed: June 9, 2022
    Publication date: December 14, 2023
    Applicant: Cypress Semiconductor Corporation
    Inventors: Hariom RAI, Arun KHAMESRA, Aniket Shashikant MATHAD
  • Patent number: 11843406
    Abstract: Example systems and methods of a wireless device use a signal attribute detector to determine a signal attribute value associated with a first frame received via a first antenna. Media access control (MAC) logic can detect that the first frame indicates an acknowledgement (ACK) of a second frame transmitted by the wireless device. Responsive to the detection of the ACK by the MAC logic, an antenna evaluator uses the signal attribute value to select one of the first antenna and the second antenna to transmit or receive a third frame.
    Type: Grant
    Filed: October 4, 2022
    Date of Patent: December 12, 2023
    Assignee: Cypress Semiconductor Corporation
    Inventor: David Hong
  • Publication number: 20230387969
    Abstract: Systems, methods, and devices select antennas to enhance the range and throughput of wireless communications devices. Methods include identifying a plurality of combinations of antennas based on a plurality of available antennas for a wireless communications device, and generating, using a processing device included in a multiple-input-multiple-output (MIMO) device, a plurality of quality metrics including at least one quality metric for each of the identified combinations of antennas, where each of the at least one quality metrics represents a signal quality of a signal associated with each of the plurality of antennas, and wherein the signal is a spatial stream. Methods further include selecting at least two antennas from the plurality of combinations of antennas based, at least in part, on the plurality of quality metrics, where the at least two antennas are selected for use by the wireless communications device during a transmitting or receiving operation.
    Type: Application
    Filed: May 26, 2023
    Publication date: November 30, 2023
    Applicant: Cypress Semiconductor Corporation
    Inventors: Prasanna Sethuraman, Visakh Asok, Paul Strauch, Rajendra Kumar Gundu Rao, Ayush Sood
  • Publication number: 20230387818
    Abstract: A primary-side-controlled fly-back converter is provided to eliminate cross-conduction between a power-switch (PS) on a primary side and a synchronous-rectifier (SR) on a secondary side when operating in continuous conduction mode (CCM). Generally, the converter includes a transformer having a primary coupled to a rectified AC input through the PS, and a secondary coupled to a DC output through the SR, the SR having a drain coupled to the secondary winding. A fly-back-controller includes a primary-controller operable to control a duty cycle of the PS, and a secondary-controller operable to turn OFF the SR when the PS turns ON in CCM. The secondary-controller includes a CCM zero-crossing-detector comparator having a first input coupled to the drain of the SR through a capacitor, and is operable to detect a sharp change in a drain voltage when the PS turns ON during CCM, and to output a signal to turn OFF the SR.
    Type: Application
    Filed: May 31, 2022
    Publication date: November 30, 2023
    Applicant: Cypress Semiconductor Corporation
    Inventors: Arun KHAMESRA, Pragyan S. BISWAL, Hariom RAI, Saravanan MURUGESAN
  • Publication number: 20230375688
    Abstract: Techniques described here introduce signature frequency modulation to unmodulated pulse signals as frequency chirps to enhance the security of multi-carrier phase-based ranging signals. The characteristics of the chirps may be mutually known by an initiator and a desired reflector of the ranging applications. The characteristics of the chirps may vary between the multi-carrier signals to thwart any attempt by an eavesdropper to predict the chirps. In one aspect, the characteristics of the chirps may be calculated for each timeslot of a ranging cycle by two authorized devices using a ciphering algorithm such as the Advanced Encryption Standard (AES) based on a shared security key. Each call of the AES may generate one or more pseudo-random numbers based on the shared security key and a time-varying initialization vector that increments every timeslot. Fields of the pseudo-random number may be extracted to determine the characteristics of the chirps associated with the timeslot.
    Type: Application
    Filed: May 19, 2022
    Publication date: November 23, 2023
    Applicant: Cypress Semiconductor Corporation
    Inventors: Nozhan HOSSEINI, Pouria ZAND, Kiran ULN, Claudio REY, Kambiz SHOARINEJAD
  • Publication number: 20230378877
    Abstract: Controlling an active clamp field effect transistor (FET) and a primary-side FET in a secondary-controlled active clamp converter is described. In one embodiment, an apparatus includes a primary-side FET coupled to a transformer and an active clamp FET disposed on a primary side of the transformer. A secondary-side controller is configured to control the active clamp FET and the primary-side FET across a same galvanic isolation barrier.
    Type: Application
    Filed: May 19, 2022
    Publication date: November 23, 2023
    Applicant: Cypress Semiconductor Corporation
    Inventors: Rejesh KARRI, Arun KHAMESRA, Hariom RAI
  • Patent number: 11821927
    Abstract: A controller includes a buck gate driver coupled to first high-side switch and first low-side switch of a buck-boost (BB) converter. A zero crossing detection (ZCD) comparator is coupled to first low-side switch. The ZCD comparator is to, while the BB converter operates in buck mode: detect zero current flow through inductor; and turn off first low-side switch in response to detecting the zero current. A boost gate driver is coupled to second high-side switch and second low-side switch of the BB converter. A reverse current detection (RCD) comparator coupled to second high-side switch. The RCD comparator is to, while the BB converter operates in boost mode: detect zero current flow through second high-side switch; and turn off second high-side switch in response to detecting the zero current.
    Type: Grant
    Filed: August 6, 2021
    Date of Patent: November 21, 2023
    Assignee: Cypress Semiconductor Corporation
    Inventors: Partha Mondal, Tudu Balia, Hariom Rai, Pulkit Shah
  • Patent number: 11825506
    Abstract: A method can include, in an access point (AP) configured to control data transfers for associated stations (STAs) in time intervals, storing a unique identifier and quality-of-service (QoS) requirement for each STA of a first set in a nonvolatile memory of the AP. In response to a STA associating with the AP, if the associating STA is in the first set, allocating time for the STA in the time intervals to meet the QoS requirement of the STA without receiving transmitted QoS data from the STA, and if the associating STA is not in the first set, establishing a QoS for the STA having a lower priority than any associated STAs of the first set. Corresponding systems and devices are also disclosed.
    Type: Grant
    Filed: August 24, 2021
    Date of Patent: November 21, 2023
    Assignee: Cypress Semiconductor Corporation
    Inventors: Hui Luo, Xianmin Wang, Hongwei Kong
  • Patent number: 11822758
    Abstract: A sense unit for inductive sensing or capacitive sensing is described. The sense unit may include a first terminal coupled to a first node, a first electrode coupled to the first node, and a second terminal. The sense unit may include a second electrode coupled to the second terminal. In a first mode, a first signal is received at the first terminal and a second signal is output on the second terminal, where the second signal may be representative of a capacitance of the sense unit. The sense unit may include an inductive coil. The sense unit may include a first capacitor. The inductive coil and the first capacitor are coupled in parallel between the first node and ground. In a second mode, a third signal is received at the first terminal and a fourth signal is output on the second terminal.
    Type: Grant
    Filed: November 23, 2021
    Date of Patent: November 21, 2023
    Assignee: Cypress Semiconductor Corporation
    Inventors: Markus Unseld, Cathal O'Lionaird, Paul Walsh, Oleksandr Hoshtanar
  • Patent number: 11816287
    Abstract: Apparatuses and methods of differential driving of adjacent electrodes for low electromagnetic interference (EMI) for scanning a touch panel are described. One apparatus generates an in-phase drive signal and an opposite-phase drive signal and applies, at a substantially same time, the in-phase drive signal to a first transmitter electrode and the opposite-phase drive signal to a second transmitter electrode adjacent to the first transmitter electrode. The apparatus receives a first sense signal from a first receiver electrode and a second sense signal from a second receiver electrode adjacent to the first receiver electrode. The apparatus combines the first sense signal and the second sense signal to obtain a third sense signal. The third sense signal represents a first self capacitance associated with the first receiver electrode. The apparatus detects a presence of an object on a touch panel using at least the first self capacitance.
    Type: Grant
    Filed: September 20, 2021
    Date of Patent: November 14, 2023
    Assignee: Cypress Semiconductor Corporation
    Inventors: Khosrov D. Sadeghipour, Brendan Lawton
  • Patent number: 11817633
    Abstract: A system and method reconfiguring an antenna for reducing and/or eliminating the effects of multipath on a phase-based measurement system. The method includes steering an antenna unit into a first direction to cause the antenna unit to generate a first constant tone (CT) signal based on a plurality of multipath signals. The method includes performing a phase measurement on the first CT signal to generate a first phase measurement value. The method includes steering the antenna unit into a second direction to cause the antenna unit to generate a second CT signal based on the plurality of multipath signals. The method includes performing a phase measurement on the second CT signal to generate a second phase measurement value. The method includes determining a change in multipath interference at the antenna unit among the plurality of multipath signals. The method includes re-steering the antenna unit into the first direction.
    Type: Grant
    Filed: August 24, 2021
    Date of Patent: November 14, 2023
    Assignee: Cypress Semiconductor Corporation
    Inventors: Zhuohui Zhang, Kiran Uln