Patents Assigned to Cypress Semiconductor
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Publication number: 20230091958Abstract: Systems, methods, and devices estimate timing values for data transmission associated with wireless communications devices. Methods include receiving, at a transceiver of a wireless communications device, at least one symbol included in a data transmission, obtaining a plurality of samples of the at least one symbol, and generating, using one or more processors, a plurality of correlation values for each of the plurality of samples. Methods further include generating, using the one or more processors, a multi-sample interpolation model based on at least some of the plurality of correlation values and determining, using the one or more processors, an estimated maximum correlation value and a temporal offset value based on the multi-sample interpolation model, the temporal offset value being used for a time of arrival computation.Type: ApplicationFiled: September 17, 2021Publication date: March 23, 2023Applicant: Cypress Semiconductor CorporationInventors: Yanbing Zhang, Hongwei Kong, Patrick Cruise
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Publication number: 20230088156Abstract: Apparatus and methods of impedance sensing are described. One method includes performing a first digital conversion of an attribute of a sensor electrode and performing a second digital conversion of the attribute of the sensor electrode. The second digital conversion differs by at least one characteristic from the first digital conversion. The method further includes calculating a resistance of the sensor electrode from a first and second digital value of the first and second digital conversions, respectively; and calculating a capacitance of the sensor electrode from the first and second digital value of the first and second digital conversions, respectively.Type: ApplicationFiled: September 27, 2022Publication date: March 23, 2023Applicant: Cypress Semiconductor CorporationInventors: Andriy MAHARYTA, Hans KLEIN, Oleksandr KARPIN, Roman OGIRKO
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Patent number: 11611969Abstract: A device can have collocated communication circuits and operate in a parallel mode if selected first wireless channels are above a certain quality, and operate in a time division (TD) mode if the selected first wireless channels are below a certain quality. The parallel mode can include using first channels for a first protocol that do not overlap a second channel used by a second protocol. The TD mode can include first time periods in which a first protocol uses first channels that overlap the second channel, while the second protocol is inactive, and second time periods, in which the first protocol is inactive and the second protocol is active.Type: GrantFiled: September 24, 2020Date of Patent: March 21, 2023Assignee: Cypress Semiconductor CorporationInventors: Raghunatha Kondareddy, Ateet Kapur
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Patent number: 11609871Abstract: An integrated circuit (IC) device according to an example includes an interconnect bus to communicate with an external memory device, wherein the interconnect bus includes a plurality of different channels to be coupled directly to a first set of masters. The IC device includes a crossbar unit to be coupled to a second set of masters, wherein the crossbar unit is to monitor bandwidth usage at the plurality of different channels, and selectively route traffic between the second set of masters and the plurality of different channels based on the monitored bandwidth usage.Type: GrantFiled: October 7, 2021Date of Patent: March 21, 2023Assignee: Cypress Semiconductor CorporationInventors: Andreas Torno, Roland Richter, Joaquin Ibanez Montemayor
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Patent number: 11609622Abstract: A multi-port Universal Serial Bus Type-C (USB-C) controller with ground and supply cable compensation technologies is described. A USB-C controller includes a first power control circuit (PCU) coupled to a system ground terminal and a first ground terminal and a second PCU coupled to the system ground terminal and a second ground terminal. The first PCU receives a first ground signal indicative of a first ground potential at a first USB-C connector and adjusts a first power voltage line (VBUS) signal on the first VBUS terminal based on the first ground signal and the system ground. The second PCU receives a second ground signal indicative of a second ground potential at a second USB-C connector and adjusts a second VBUS signal on the second VBUS terminal based on the second ground signal and the system ground.Type: GrantFiled: May 12, 2021Date of Patent: March 21, 2023Assignee: Cypress Semiconductor CorporationInventors: Pulkit Shah, Hariom Rai
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Publication number: 20230079027Abstract: Systems, methods, and devices perform unified demodulation operations for wireless communications devices. Methods may include receiving, at a buffer of a wireless communications device, a data packet, and performing, using a processing device, one or more synchronization operations based on one or more operational modes of a wireless communications protocol. Methods may additionally include identifying, using the processing device, a type of the data packet, configuring, using the processing device, a receive chain of the wireless communications device to perform a type of demodulation operation based on the identified type of the data packet.Type: ApplicationFiled: September 15, 2021Publication date: March 16, 2023Applicant: Cypress Semiconductor CorporationInventors: Yanbing Zhang, Hongwei Kong, Patrick Cruise
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Publication number: 20230080736Abstract: Implementations disclosed describe methods, devices, and systems to perform out-of-distribution and recognition of activities using an inertial measurement unit (IMU) sensor. A method may include receiving motion data by a device from a motion sensor. The method further includes generating image data comprising one or more images based on the motion data. The method further includes determining that a first portion of the image data corresponds to activities outside a classification distribution. The method further includes filtering the image data by removing the first portion from the image and generating filtered image data. The method further includes determining an activity classification, within the classification distribution, based on the filtered image data. The method further includes modifying an operating parameter of the device based on the activity classification.Type: ApplicationFiled: August 11, 2022Publication date: March 16, 2023Applicant: Cypress Semiconductor CorporationInventors: Niall LYONS, Avik SANTRA, Ashutosh PANDEY
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Publication number: 20230081229Abstract: Disclosed are techniques for saving power in a Universal Serial Bus (USB) repeater/re-timer between a USB host and a peripheral device by intercepting packets received from the host to predict the direction of data traffic to selectively turn off/on circuitry of a peripheral port used to receive packets from the peripheral device. If a host port determines that the host is sending a start-of-frame (SOF) packet, the direction of data flow is from the host to the peripheral device, and the repeater may turn off the peripheral port such as squelch circuitry. If the host port determines that the host is sending a non-SOF packet, such as an address token that precedes a host-to-peripheral-device data transfer or a peripheral-device-to-host data transfer, the direction of data flow is anticipated to be from the peripheral device to the host, and the repeater may re-enable the deactivated circuitry of the peripheral port.Type: ApplicationFiled: November 17, 2022Publication date: March 16, 2023Applicant: Cypress Semiconductor CorporationInventors: Pradeep Kumar Bajpai, Godwin Gerald Arulappan, Anup Nayak
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Patent number: 11606042Abstract: A secondary side controller of a flyback AC-DC converter includes an integrated circuit, which includes: an analog-to-digital converter (ADC) coupled to a voltage bus (VBUS), the ADC to output a digital value corresponding to a voltage level of the VBUS; first logic configured to generate a reference voltage based on the digital value; second logic configured to generate a VBUS gain value based on output power of a flyback transformer of the flyback AC-DC converter; an integrator to accumulate current corresponding to a sensed voltage at a drain of a synchronous rectifier (SR) of a secondary side of the flyback transformer, the accumulated current to be modified according to the VBUS gain value, wherein the integrator outputs an updated sensed voltage; and a comparator to output a detection signal, indicative of a negative sense voltage, in response to the updated sensed voltage matching the reference voltage.Type: GrantFiled: January 14, 2022Date of Patent: March 14, 2023Assignee: Cypress Semiconductor CorporationInventors: Partha Mondal, Rajesh Karri, Hariom Rai
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Patent number: 11605364Abstract: Systems, methods, and devices implement line-based rendering of graphics. Methods include receiving a command associated with graphical data, the command identifying a plurality of pixel mapping operations to be implemented on a plurality of data objects included in the graphical data. Methods also include determining a plurality of rendering parameters, the plurality of rendering parameters identifying a partitioning of the graphical data into a plurality of portions, and further identifying a pixel mapping operation for each of the plurality of portions. Methods further include generating a plurality of sub-commands based, at least in part, on the plurality of rendering parameters and the command, the plurality of sub-commands identifying a processing operation for each data object included in each of the plurality of portions of the graphical data. Methods also include implementing a processing operation for at least one portion based on at least some of the plurality of sub-commands.Type: GrantFiled: May 19, 2021Date of Patent: March 14, 2023Assignee: Cypress Semiconductor CorporationInventors: Peter Kirst, Andreas Torno, Roland Richter
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Publication number: 20230071912Abstract: Apparatuses and methods of capacitance-to-digital code conversion are described. One apparatus includes a bridge circuit and a modulator front-end circuit. The bridge circuit includes a first terminal to couple to a reference cell and a second terminal to couple to a sensor cell. The modulator front-end circuit includes a comparator coupled to the bridge circuit, a first modulation capacitor coupled to a first input of the comparator, and a second modulation capacitor coupled to a second input of the comparator. The modulator front-end circuit provides a digital bitstream. A duty cycle of the digital bitstream is representative of a ratio between a capacitance of the sensor cell and a reference capacitance of the reference cell.Type: ApplicationFiled: September 2, 2022Publication date: March 9, 2023Applicant: Cypress Semiconductor CorporationInventor: Andriy MAHARYTA
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Publication number: 20230075274Abstract: A method, apparatus, and system for providing temporary access point (AP) functionality to an intermediary device to provide wireless network credentials to a wireless device (STA) to be connected to a wireless network including an AP is described. The intermediary device may mimic the AP to provide wireless network credentials to the wireless device and discontinue an onboarding session to allow the wireless device to access the AP directly.Type: ApplicationFiled: February 27, 2020Publication date: March 9, 2023Applicant: Cypress Semiconductor CorporationInventors: Vinayak Kamath, Dhruvaraja Kunjar, Pramod Prakash Kanni
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Patent number: 11601832Abstract: Disclosed are methods and systems for delaying packet transmissions over a wireless communication channel until a more favorable channel condition is detected. A device may measure a channel metric when it receives periodic beacon signals. The device may compare the channel metric against a programmed metric threshold. If the channel metric is less than the metric threshold, the device may delay the transmission of a packet until a later transmission window or transmit opportunity (TXOP) when the channel metric rises above the metric threshold, indicating the presence of a more favorable condition for transmission, or until a preconfigured timeout period elapses before the more favorable condition is found.Type: GrantFiled: July 16, 2021Date of Patent: March 7, 2023Assignee: Cypress Semiconductor CorporationInventors: Prasanna Kumar Sethuraman, Rajendra Kumar Gundu Rao, Ayush Sood, Paul Strauch
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Publication number: 20230064650Abstract: A system and method reconfiguring an antenna for reducing and/or eliminating the effects of multipath on a phase-based measurement system. The method includes steering an antenna unit into a first direction to cause the antenna unit to generate a first constant tone (CT) signal based on a plurality of multipath signals. The method includes performing a phase measurement on the first CT signal to generate a first phase measurement value. The method includes steering the antenna unit into a second direction to cause the antenna unit to generate a second CT signal based on the plurality of multipath signals. The method includes performing a phase measurement on the second CT signal to generate a second phase measurement value. The method includes determining a change in multipath interference at the antenna unit among the plurality of multipath signals. The method includes re-steering the antenna unit into the first direction.Type: ApplicationFiled: August 24, 2021Publication date: March 2, 2023Applicant: Cypress Semiconductor CorporationInventors: Zhuohui Zhang, Kiran Uln
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Publication number: 20230061086Abstract: Systems, methods, and devices implement supplemental scanning for establishing network connections in wireless networks. Methods include sending a request to a wireless device, the request including a plurality of scanning parameters, the plurality of scanning parameters identifying a plurality of requested wireless network parameters. Methods also include receiving a reply from the wireless device, the reply including a result of one or more scanning operations performed based on the plurality of scanning parameters. Methods further include selecting, using one or more processors, one or more network connection operations based, at least in part, on the result of the one or more scanning operations, the one or more network connection operations identifying a timing relative to a plurality of wireless projection packets. Methods additionally include performing, using the one or more processors, the one or more network connection operations based, at least in part, on the identified timing.Type: ApplicationFiled: September 1, 2021Publication date: March 2, 2023Applicant: Cypress Semiconductor CorporationInventors: Alan Merlock, Greg Gangitano, Kenneth Lap-Yu Ma, Bradley Evans
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Publication number: 20230063442Abstract: Disclosed are methods and systems for a Bluetooth Low Energy (BLE) receiver to reduce the number of retransmission of packets needed to receive an error free packet so as to improve channel throughput. Techniques to reduce the number of retransmissions include a combination of processing of the header of the received packets to increase the number of corrupted packets available for reconstructing the original payload and bit error correction (BEC) of the payload of the corrupted packets. Header processing may include making available for payload reconstruction a packet whose received access address differs by no more than 1-bit from an assigned address of the receiver provided at least one of the corrupted packets used in the reconstruction contains an error-free access address. Header processing may also include using a prior error-free decoded length of the packet to aid in the determination of the length field of a current packet.Type: ApplicationFiled: September 2, 2022Publication date: March 2, 2023Applicant: Cypress Semiconductor CorporationInventor: Robert Zopf
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Patent number: 11595048Abstract: A digital phase-locked loop (DPLL) includes a time-to-digital converter (TDC) to generate a multi-bit code based on a phase error between a reference clock and a feedback clock, a digital loop filter (DLF) coupled to the TDC, a digitally-controlled oscillator (DCO) circuit coupled to the DLF and to generate an output signal that is convertible to the feedback clock, and a logic component coupled to an input of the DCO circuit. The logic component is to: trigger, in response to detecting a power on of the DPLL circuit, a switch to decouple the DLF from the DCO circuit; determine, from the reference clock, a target frequency; measure a frequency of the feedback clock; and iteratively generate, based on the frequency during each iteration, a set of digital bits to the input of the DCO circuit that successively causes the frequency to converge towards the target frequency.Type: GrantFiled: March 25, 2022Date of Patent: February 28, 2023Assignee: Cypress Semiconductor CorporationInventor: Avri Harush
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Patent number: 11595783Abstract: A system and method for an efficient secure phase-based ranging using loopback calibration, including receiving, by a reflector during a current timeslot, an incoming constant tone (CT) signal having a phase shift; determining, by the reflector during the current timeslot or a previous timeslot, a phase shift correction value by using a receiver/transmitter (Rx/Tx) loopback path of the reflector; and/or generating, by the reflector, an outgoing CT signal having an updated phase shift by adjusting the phase shift of the incoming CT signal based on the phase shift correction value.Type: GrantFiled: June 7, 2021Date of Patent: February 28, 2023Assignee: Cypress Semiconductor CorporationInventors: Yan Li, Jie Lai, Pouria Zand, Kiran Uln, Victor Simileysky
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Patent number: 11595972Abstract: A method can include at a combination device, receiving or generating a slot availability mask (SAM) information compatible with a Bluetooth and/or Bluetooth Low Energy (BT) standard; by operation of BT compatible circuits of the combination device, determining a schedule of BT compatible data transfers in response to at least the SAM information; and by operation of circuits compatible with at least one IEEE 802.11 wireless standard (WLAN circuits), determining a schedule of WLAN compatible data transfers in response to at least the SAM information. Related systems and methods are also disclosed.Type: GrantFiled: September 20, 2019Date of Patent: February 28, 2023Assignee: Cypress Semiconductor CorporationInventors: Raghunatha Kondareddy, Kamesh Medapalli
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Patent number: 11594961Abstract: An apparatus includes a controller. The controller monitors a magnitude of first current supplied by an output voltage of a first power converter to power a dynamic load. The controller controls a second power converter to supply second current through the dynamic load based on the monitored magnitude of first current.Type: GrantFiled: July 19, 2021Date of Patent: February 28, 2023Assignees: Infineon Technologies Austria AG, Cypress Semiconductor (Canada), Inc.Inventors: Darryl Tschirhart, Danny Clavette