Patents Assigned to Cypress Semiconductor
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Publication number: 20220408313Abstract: Implementations disclosed describe techniques and systems to facilitate efficient operations of wireless networks organized in a topology of communicating nodes. Techniques include cascade synchronization of various nodes of the network by generating and maintaining a common time using times associated with ordered communications between nodes. The common time maintained by the network allows performance of synchronous action for precise industrial, medical, and testing applications. The described techniques and systems further include management of communication windows between different nodes in a way that facilitates fast and efficient propagation of data collected by the network from multiple source nodes to one or more destination nodes.Type: ApplicationFiled: December 30, 2021Publication date: December 22, 2022Applicant: Cypress Semiconductor CorporationInventors: Manamohan D. Mysore, Ash Kapur, Victor Zhodzishsky
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Publication number: 20220408448Abstract: Implementations disclosed describe techniques and systems to facilitate efficient operations of wireless networks organized in a topology of communicating nodes. Techniques include cascade synchronization of various nodes of the network by generating and maintaining a common time using times associated with ordered communications between nodes. The common time maintained by the network allows performance of synchronous action for precise industrial, medical, and testing applications. The described techniques and systems further include management of communication windows between different nodes in a way that facilitates fast and efficient propagation of data collected by the network from multiple source nodes to one or more destination nodes.Type: ApplicationFiled: December 30, 2021Publication date: December 22, 2022Applicant: Cypress Semiconductor CorporationInventors: Manamohan D. Mysore, Ash Kapur, Victor Zhodzishsky, James Wihardja
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Publication number: 20220408370Abstract: A method can include at a first station in a wireless network, receiving path loss (PL) transmissions from at least a second station, dynamically changing power for transmissions from the first station to the second station based on the received PL information, determining PL values for transmissions received at the first station from other stations, and sending PL transmissions from the first station that include the determined PL values for at least one other station. The PL transmissions are configured to be received by stations of the same wireless network and stations of a different wireless network. Corresponding devices and systems are also disclosed.Type: ApplicationFiled: July 26, 2022Publication date: December 22, 2022Applicant: Cypress Semiconductor CorporationInventors: Xianmin WANG, Hui LUO, Hongwei KONG
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Publication number: 20220408382Abstract: Implementations disclosed describe techniques and systems to facilitate efficient operations of wireless networks organized in a topology of communicating nodes. Techniques include cascade synchronization of various nodes of the network by generating and maintaining a common time using times associated with ordered communications between nodes. The common time maintained by the network allows performance of synchronous action for precise industrial, medical, and testing applications. The described techniques and systems further include management of communication windows between different nodes in a way that facilitates fast and efficient propagation of data collected by the network from multiple source nodes to one or more destination nodes.Type: ApplicationFiled: December 30, 2021Publication date: December 22, 2022Applicant: Cypress Semiconductor CorporationInventors: Manamohan D. Mysore, Ash Kapur, Michael Chandler, Victor Zhodzishsky
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Patent number: 11531080Abstract: An example method for estimating the angle-of-arrival (AoA) and other parameters of radio frequency (RF) signals that are received by an antenna array comprises: receiving a plurality of radio frequency (RF) signal power measurements by a plurality of antenna elements at a plurality of RF channels; computing, by applying a machine learning model to the plurality of RF signal power measurements, an estimated RF signal parameter value; and outputting the RF signal parameter value.Type: GrantFiled: September 26, 2019Date of Patent: December 20, 2022Assignee: Cypress Semiconductor CorporationInventors: Aidan Smyth, Victor Simileysky, Kiran Uln
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Patent number: 11533687Abstract: A method can include an integrated circuit device, determining if first communication circuits are operating in a first mode that wirelessly receives data at a first rate or a second mode that wirelessly receives data at a second rate that is lower than the first rate. If the first communication circuits are operating in the second mode, transmitting signals with the second communication circuits at a first power level, and if operating in the first mode, transmitting signals with the second communication circuits at a second power level that is lower than the first power level. In the first mode, X symbols per data bit are received and in the second mode, Y symbols per data bit are received, where X<Y. Corresponding devices and methods are also disclosed.Type: GrantFiled: September 25, 2020Date of Patent: December 20, 2022Assignee: Cypress Semiconductor CorporationInventor: Raghunatha Kondareddy
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Patent number: 11531424Abstract: An asynchronous capacitance-to-digital converter (CDC) is described that allows for very low-power operation when during inactive periods (when no conductive object is in contact or proximity to the sensing electrodes). Asynchronous operation of the CDC provides for capacitance-to-digital conversion without the use of system resources and more power intensive circuit elements.Type: GrantFiled: March 28, 2018Date of Patent: December 20, 2022Assignee: Cypress Semiconductor CorporationInventors: Paul M. Walsh, Dermot MacSweeney, Said Hussaini, Hui Jiang, Kofi Makinwa
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Patent number: 11533055Abstract: Implementations disclosed describe a programmable analog subsystem (PASS) having a plurality of reconfigurable analog circuits. The PASS may be coupled to an input/output device to receive an input signal and to an interface to communicate data with a central processing unit. In a first PASS configuration, with the plurality of reconfigurable analog circuits having a first configuration setting, the PASS may process the input signal through the plurality of reconfigurable analog circuits to generate a first output value based on the input signal. Responsive to the first output value, the PASS may reconfigure the plurality of reconfigurable analog circuits into a second PASS configuration having a second configuration setting, such that the second configuration setting is different than the first configuration setting.Type: GrantFiled: March 29, 2019Date of Patent: December 20, 2022Assignee: Cypress Semiconductor CorporationInventors: Eashwar Thiagarajan, Andrew Page, Harold Kutz, Kendall Castor-Perry, Rajiv Singh, Erhan Hancioglu, Bert Sullam
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Patent number: 11531435Abstract: Technology directed to low-emissions touch controller in in-cell touch display systems is described. One in-cell touch controller includes a signal generator circuit that is configured to generate a sense signal according to a sensing function, the sense signal including a windowed sinusoidal waveform. The controller generates a transition signal to transition the in-cell touch display between a display function and the sensing function. The controller drives the sense signal and the transition signal on common voltage (VCOM) layer of electrodes during a touch scanning interval. During a display function interval an integrated display driver is configured to drive a first signal on the VCOM layer of electrodes during a display function interval.Type: GrantFiled: January 14, 2022Date of Patent: December 20, 2022Assignee: Cypress Semiconductor CorporationInventors: Viktor Kremin, Oleksandr Pirogov, Jens Weber, Yarsolav Lek, Daniel O'Keeffe, Brendan Lawton, Khosrov D Sadeghipour, Gaurav Panchanan, Andrew Kinane
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Patent number: 11528095Abstract: Disclosed are techniques for removing dribble bits following the end-of-packet (EOP) of a High-Speed data packet inserted by the transmission envelope detector of a repeater/hub that interconnects electronic devices compliant with Universal Serial Bus (USB) Specification Revision 2.0 or higher. A physical layer logic (PHY) of a first port of the repeater/hub receives a High-Speed data packet to store a recovered bit stream into an elastic buffer. The recovered bit stream may include dribble bits inserted by the PHY after the EOP. The repeater/hub reads the recovered bit stream from the elastic buffer for transmission through the PHY of a second port. The repeater/hub monitors the EOP. When the EOP is detected, the repeater/hub prevents transmission of the dribble bits of the recovered bit stream following the EOP from the second port, eliminating the intended receiver of the High-Speed data packet from the complexity of dealing with dribble bits.Type: GrantFiled: December 11, 2020Date of Patent: December 13, 2022Assignee: Cypress Semiconductor CorporationInventors: Godwin Gerald Arulappan, Pradeep Kumar Bajpai
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Patent number: 11528663Abstract: Systems, methods, and devices suspend and establish wireless communications connections. Methods include determining a wireless communications device should be transitioned to operate in a first mode of operation, and transitioning first logic of the wireless communications device to operate in the first mode of operation using second logic of the wireless communications device, the first logic implementing a host stack of a Bluetooth protocol, the second logic implementing a controller stack of the Bluetooth protocol, the transitioning of the first logic to operate in the first mode of operation including disconnecting a communications connection.Type: GrantFiled: June 3, 2021Date of Patent: December 13, 2022Assignee: Cypress Semiconductor CorporationInventors: Balasubramanyam Rangineni, Rohit Gupta
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Patent number: 11527957Abstract: A mode-transition architecture for USB Type-C controllers is described herein. In an example embodiment, an integrated circuit (IC) controller includes controller includes a controller coupled to a slope compensation circuit, the controller to cause the slope compensation circuit to apply a first slope compensation to the input current in a first mode in which the buck-boost converter is operating in a discontinuous conduction mode (DCM). The controller detects a transition of the buck-boost converter from a first mode having a first duty cycle to a second mode and causes the slope compensation circuit to apply a second slope compensation to the input current. The second slope compensation starts at a maximum offset of the first slope compensation.Type: GrantFiled: January 13, 2021Date of Patent: December 13, 2022Assignee: Cypress Semiconductor CorporationInventors: Rajesh Karri, Arun Khamesra, Pulkit Shah, Hariom Rai
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Publication number: 20220394490Abstract: The embodiments described herein are directed at techniques to sharing a transmission medium in a Bluetooth transceiver/WLAN transceiver combination device. A first device may receive a request from a second device to use the wireless transmission medium. The second device may also transmit timing data to the first device. The first device may determine a period of time to allow the second device to use the wireless transmission medium based on the timing data.Type: ApplicationFiled: June 7, 2021Publication date: December 8, 2022Applicant: Cypress Semiconductor CorporationInventors: Munukutla Sandeep Sarma, Raghavendra Kencharla
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Publication number: 20220394424Abstract: A system and method for an efficient secure phase-based ranging using loopback calibration, including receiving, by a reflector during a current timeslot, an incoming constant tone (CT) signal having a phase shift; determining, by the reflector during the current timeslot or a previous timeslot, a phase shift correction value by using a receiver/transmitter (Rx/Tx) loopback path of the reflector; and/or generating, by the reflector, an outgoing CT signal having an updated phase shift by adjusting the phase shift of the incoming CT signal based on the phase shift correction value.Type: ApplicationFiled: June 7, 2021Publication date: December 8, 2022Applicant: Cypress Semiconductor CorporationInventors: Yan Li, Jie Lai, Pouria Zand, Kiran Uln, Victor Simileysky
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Patent number: 11523338Abstract: A method can include negotiating a target wake time (TWT) with a TWT session period (TWT SP) duration and generating mask data that inhibits communications according to a second standard during at least a portion of TWT SP. A method can further include, by operation of second communication circuits, generating a communications mask from mask data received from WLAN circuits, in response to the timing signal, synchronizing the communications mask with the TWT SP, and in response to the communications mask, inhibiting communications according to the second standard during at least a portion of the TWT SP. Corresponding devices and systems are also disclosed.Type: GrantFiled: December 17, 2020Date of Patent: December 6, 2022Assignee: Cypress Semiconductor CorporationInventors: Wenyu Liu, Raghunatha Kondareddy, Xianmin Wang
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Patent number: 11521962Abstract: An electrostatic discharge protection circuit capable of clamping both positive and negative ESD events and passing signals is provided. Generally, the circuit includes a p-channel field-effect transistor (PFET) clamp coupled to a pin to be protected, the PFET clamp including a plurality of PFETs in a DN-well, an n-channel field-effect transistors (NFET) clamp coupled between ground and the pin through the PFET clamp, the NFET clamp including a plurality of NFETs coupled in series, and a bias network for biasing a voltage of the DN well to substantially equal a voltage on the pin when the voltage on the pin is greater than ground potential, and to ground potential when the pin voltage is less than ground potential. The plurality of are PFETs coupled in parallel between the pin and the NFET clamp, each of the PFETs is coupled to the pin though one of a plurality ballast resistors.Type: GrantFiled: September 14, 2021Date of Patent: December 6, 2022Assignee: Cypress Semiconductor CorporationInventors: David Michael Rogers, Eric N. Mann, Eric Lee Swindlehurst, Toru Miyamae, Timothy John Williams, Ryuta Nagai, Sungkwon Lee, Ravindra M. Kapre, Mimi Xuefeng Zhao Qian, Yan Yi, Dung Si Ho, Boo Chin-Hua
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Patent number: 11522458Abstract: An apparatus includes a first high-side driver of a buck-boost converter, the first high-side driver powered between a first bootstrap voltage (VBST1) and a first output voltage of a first high-side switch driven by the first high-side driver. A second high-side driver is powered between a second bootstrap voltage (VBST2) and a second output voltage of a second high-side switch driven by the second high-side driver. A comparator is to detect VBST1 drop below a threshold value with respect to the first output voltage when the buck-boost converter is in boost mode. A leakage control circuit is to boost, using VBST2 as a voltage source, VBST1 each cycle of boost mode in which an output of the comparator is enabled.Type: GrantFiled: May 13, 2021Date of Patent: December 6, 2022Assignee: Cypress Semiconductor CorporationInventors: Hemant Prakash Vispute, Partha Mondal, Pulkit Shah, Hariom Rai
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Publication number: 20220385250Abstract: Embodiments of the present disclosure provide a chopper amplifier circuit that includes an operational amplifier, and a notch filter to be operated by a chopping pulse. The notch filter has a first branch that has a first capacitor, and a second branch that has a second capacitor. A chopping delay switch is connected to the first branch and the second branch of the notch filter. A control circuit is to close the chopping delay switch to short-circuit the first branch and the second branch of the notch filter to each other. The control circuit is to detect establishment of feedback signal at the chopper amplifier. The control circuit is to open the chopping delay switch, responsive to detecting establishment of the feedback signal at the chopper amplifier.Type: ApplicationFiled: May 25, 2021Publication date: December 1, 2022Applicant: Cypress Semiconductor CorporationInventor: Katsuyuki Yasukouchi
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Publication number: 20220382451Abstract: Apparatuses and methods of multi-phase scanning of a touch panel are described. One apparatus selects a sequence having a number of one values, negative one values, and zero values. The one values correspond to an in-phase drive signal, the negative one values correspond to an opposite-phase drive signal, and the zero values correspond to a reference signal (e.g., reference voltage or ground). A sum of the sequence is equal to zero. The apparatus applies one of the in-phase drive signal, the opposite-phase drive signal, or the reference signal to each of a first set of electrodes at a first stage according to the sequence. The apparatus rotates the sequence to obtain a rotated sequence and applies one of the signals according to the rotated sequence. The apparatus receives sense signals to detect a presence of an object on the touch panel.Type: ApplicationFiled: May 26, 2021Publication date: December 1, 2022Applicant: Cypress Semiconductor CorporationInventors: Volodymyr Bihday, Andriy Maharyta, Igor Kravets, Mykhaylo Krekhovetskyy, Ihor Musijchuk
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Patent number: 11513584Abstract: Disclosed are techniques for saving power in a Universal Serial Bus (USB) repeater/re-timer between a USB host and a peripheral device by intercepting packets received from the host to predict the direction of data traffic to selectively turn off/on circuitry of a peripheral port used to receive packets from the peripheral device. If a host port determines that the host is sending a start-of-frame (SOF) packet, the direction of data flow is from the host to the peripheral device, and the repeater may turn off the peripheral port such as squelch circuitry. If the host port determines that the host is sending a non-SOF packet, such as an address token that precedes a host-to-peripheral-device data transfer or a peripheral-device-to-host data transfer, the direction of data flow is anticipated to be from the peripheral device to the host, and the repeater may re-enable the deactivated circuitry of the peripheral port.Type: GrantFiled: March 4, 2021Date of Patent: November 29, 2022Assignee: Cypress Semiconductor CorporationInventors: Pradeep Kumar Bajpai, Godwin Gerald Arulappan, Anup Nayak