Abstract: A system and method for virtualizing external pins and their internal functions within a microprocessor employing an operating system independent interrupt and N subhandlers to virtual the equivalent functions of the pins ordinarily performed by extrinsic circuitry internal to the microprocessor.

Abstract: A processor for outputting processor state information during idle bus cycles to facilitate the diagnosing and debugging of a processor. The processor includes a plurality of external pins for communicating data from the processor; a visibility register for selecting one of a plurality of modes which identifies processor state information to output onto the plurality of external pins; and a bus interface unit for communicating data to the external pins of the processor and for detecting an idle bus cycle. The bus interface unit outputs processor state information according to the identified mode onto the plurality of external pins in response to detecting an idle bus cycle.

Abstract: A prefetch unit is used, in an exemplary embodiment, in a superscalar, superpipelined microprocessor compatible with the x86 instruction set architecture. Normally, the prefetch unit performs split prefetching by generating low and high prefetch addresses in a single clock, with the high prefetch address being generated from the low prefetch address by incrementation. In cases where the low prefetch address is supplied to the prefetch unit too late in a clock period to generate the high prefetch address, such as where a branch instruction is not detected by a branch processing unit so that the target instruction address (i.e., the low prefetch address) is supplied by an address calculation stage, the prefetch unit generates a prefetch request consisting of only the low prefetch address.

Abstract: In a pipelined processor having at least one execution pipeline for executing instructions, the execution pipeline including ID (decode), AC (address calculation), and EX (execution) processing stages, the processor capable of addressing segments of system memory coupled thereto, a circuit for, and method of, setting a segment access indicator associated with a segment of the system memory being accessed by the processor. The circuit includes: (a) exception generating circuitry to generate an exception when the segment access indicator requires setting and (b) exception handling circuitry, invoked by the processor in response to generation of the exception, to flush the execution pipeline of instructions following a segment load instruction, set the segment access indicator and load an address pointer of the processor with an address corresponding to a specified location within the segment.

Abstract: In a pipelined processor having at least one execution pipeline for executing instructions, the execution pipeline including ID (decode), AC (address calculation), and EX (execution) processing stages to process instructions for the processor, the processor including a register translation system that controls a renaming of physical registers of the processor to logical registers thereof, a tracking circuit that tracks availability of the physical registers for the renaming, method of operation thereof and processor containing the same.

Abstract: Independent functional units are clocked by a clock source generator having at least two adjustable delay lines for independently adjusting the duty cycles of at least two clocks so that speed path margins are individually optimized for each functional unit.

Abstract: A microarchitecture in a complex instruction computer system is disclosed employing a sparse microROM array and concatenation address circuitry for forming microaddress entry points, avoiding the need for a programmable logic array to translate instruction opcodes and avoiding duplicative entry points, thus minimizing the microROM array size.

Abstract: An enhanced system management mode (SMM) includes nesting of SMI (system management interrupt) routines for handling SMI events. Enhanced SMM is implemented in an computer system to support a Virtual System Architecture (VSA) in which peripheral hardware, such as for graphics and/or audio functions, is virtualized (simulated by SMI routines). Reentrant VSA/SMM software (handler) includes VSA/SMI routines invoked either by (a) SMI interrupts, such as from non-virtualized peripheral hardware such as audio FIFO buffers, or (b) SMI traps, such as from accesses to memory mapped or I/O space allocated to a virtualized peripheral function. SMI nesting permits a currently active VSA/SMI routine to be preempted by another (higher priority) SMI event. The SMM memory region includes an SMI header segment and a VSA/SMM software segment--the SMI header segment is organized as a quasi-stack into which nested SMI headers are saved.

Abstract: An address translation unit is disclosed employing a direct-mapped translation lookaside buffer and a relatively small, associative victim translation lookaside buffer for translating linear addresses to physical addresses expediently and avoiding thrashing, without requiring large amounts of hardware and space.

Abstract: An input buffer circuit provides programmable resistors for inputs to a microprocessor and compensates for switching voltage timing differences caused when a selected programmable resistor is utilized for a selected input. In a preferred embodiment, an input buffer circuit has a weak transistor coupled between the input and an operating voltage source or ground, and a compensation circuit including two transistors in series between the operating voltage source or ground, and an output. When the weak transistor is on, thereby raising or lowering the input signal, one of the transistors is also on and the other transistor couples the output to the operating voltage source or ground.

Abstract: In an .chi.86-compatible processor capable of operating in a protected mode of operation in which privilege levels are assigned to tasks executing therein, an application task being assigned a lowest privilege level and executable in the processor to cause the processor to calculate addresses corresponding to specific locations in a computer memory associated with the processor, the addresses to be in alignment with respect to the computer memory prior to the processor issuing the addresses, a circuit for, and method of, handling sequential alignment faults and a computer system embodying the same.

Abstract: A processing system includes clock circuitry that statically multiplies/divides a stimulus signal which can then be removed while a resultant product clock is still generated, A cascaded--dual tap delay line is employed having a single phase inversion which is looped back and logically ORed with the first edge of the stimulus signal to induce oscillation. A multiplier/divisor control signal adjusts the "N" times multiplication by disabling the loop after the desired number of pulses is achieved within the period of the stimulus signal. 1/M multiplication is achieved by disabling the loop from oscillating for M stimulus clocks. Multiple frequencies can be dynamically realized on-the-fly without resynchronization by combining delayed clock pulses with a multiplexer.

Abstract: A branch processing unit (BPU) is used, in an exemplary embodiment, in a superscalar, superpipelined microprocessor compatible with the x86 instruction set architecture. In one embodiment, the BPU includes a target cache and a separate far target cache--the far target cache stores limits and mode bits for far targets stored in the target cache. For each far COF entry in the target cache, an FTC index field stores an index pointing to the corresponding entry in the far target cache. For far COFs that hit in the target cache, the target cache outputs corresponding far target addressing information and the associated FTC index to indirectly access the far target cache to obtain the associated segment limit information.

Abstract: A superscalar superpipelined microprocessor having a write buffer located between the core and cache is disclosed. The write buffer is controlled to store the results of write operations to memory until such time as the cache becomes available, such as when no high-priority reads are to be performed. The write buffer includes multiple entries that are split into two circular buffer sections for facilitating the interaction with the two pipelines of the core; cross-dependency tables are provided for each write buffer entry to ensure that the data is written from the write buffer to memory in program order, considering the possibility of prior data present in the opposite section. Non-cacheable reads from memory are also ordered in program order with the writing of data from the write buffer. Features for handling speculative execution, detecting and handling data dependencies and exceptions, and performing special write functions (misaligned writes and gathered writes) are also disclosed.

Abstract: Bidirectional handshake protocol circuitry is provided for asserting and deasserting a signal across a single line between a first device and a second device. Only the first device is permitted to assert the signal on the single line; and only the second device is permitted to deassert the signal on the single line. The protocol is particularly useful between a chipset and a CPU where the chipset asserts a System Management Interrupt (SMI) and the CPU deasserts the interrupt to signal to the chipset that the service routine is complete. After assertion (or deassertion), there is an overlap or hand-off period whereby the single line is driven in the same direction by both devices. After a predetermined number of clock cycles, the device which asserted or deasserted the signal is tristated to await deassertion or assertion, respectively.

Abstract: A pipelined x86 processor includes a prefetch unit (prefetch buffer) and a branch unit that cooperate to detect when the target of a branch (designated a short branch) is already in the prefetch buffer, thereby avoiding issuing a prefetch request to retrieve the target. The branch unit includes a branch target cache (BTC) in which each entry stores, in addition to target address information for prefetching a prefetch block of instruction bytes containing a target instruction, a prefetch block location field--when this field is valid, it provides the location of the target instruction for a short branch within a prefetch block that is already in the prefetch buffer. In response to a branch that hits in the BTC, if the associated prefetch block location field is valid, the prefetch unit is able to begin transferring instruction bytes for the target instruction without issuing a prefetch request for the prefetch block containing the target instruction.

Abstract: A branch processing unit (BPU) is used, in an exemplary embodiment, in a superscalar, superpipelined microprocessor compatible with the x86 instruction set architecture. The BPU implements a branch prediction scheme using a target cache and a separate history cache. The target cache stores target addressing information and history information for predicted taken branches. The history cache stores history information only for predicted not-taken branches. The exemplary embodiment uses a two-bit prediction algorithm such that the target cache and the history cache need only story a single history bit (to differentiate between strong and weak states of respectively predicted taken and not-taken branches).

Abstract: A branch processing unit (BPU) is used, in an exemplary embodiment, in a superscalar, superpipelined microprocessor compatible with the x86 instruction set architecture. The BPU includes a target cache organized in banks to support split prefetching. Prefetch requests (addressing a prefetch block of 16 bytes) are separated into low and high block addresses (addressing split blocks of 8 bytes). The low and high block addresses differ in bit position ?3! designated a bank select bit, where the low block address of an associated prefetch request may be designated by a ?1 or 0! such that a split block associated with a low block address may be allocated into either bank of the target cache (i.e., the low block of a prefetch request can start on an 8 byte alignment rather than the 16 byte alignment).

Abstract: A method of data communication between asynchronous processes of a computer system is disclosed in connection with a cache coherency system for a processor-cache used in a multi-master computer system in which bus arbitration signals either are not available to the processor-cache, or are not exclusively relied on by the processor-cache to assure validity of the data in the cache (e.g., a 386-bus compatible computer system using an external secondary cache in which bus arbitration signals are only connected to and used by the secondary cache controller). In an exemplary external-chip implementation, the cache coherency system (120) comprises two PLAs--a FLUSH module (122) and a WAVESHAPING module (124). The FLUSH module (a) receives selected bus cycle definition and control signals from a microprocessor ((110), (b) detects FLUSH (cache invalidation) conditions, i.e., bus master synchronization events, and for each such FLUSH condition, (c) provides a FLUSH output signal.

Abstract: A branch processing unit (BPU) is used, in an exemplary embodiment, in a superscalar, superpipelined microprocessor compatible with the x86 instruction set architecture. The BPU includes a return stack for call/returns, including return stack pointer repair in the case of the failure of a call/return to confirm (decode) or resolve. Return stack control logic maintains a return stack pointer, incrementing and decrementing the return stack pointer respectively for call/return pairs that hit in the target cache--in addition, the return stack control logic maintains two additional stack pointers used for repair: (a) a confirmation pointer that is incremented when a call is decoded and decremented when a return is decoded; and (b) a resolution pointer that is incremented when a call resolves, and decremented when a return resolves.