Abstract: A component carrier and mating system is disclosed for aligning and mating closely spaced leads of integrated circuit (IC) packages, which protects the integrated circuit packages and permits easy installation. The system is particularly adapted for aligning and mating integrated circuits which have high pin counts. A carrier assembly aligns for mating and interconnecting at least two integrated circuit packages having a plurality of leads extending from the packages. A protective shroud covers the stacked packages to maintain the packages in electrical and mechanical engagement and to assure that no damage occurs to the integrated circuit packages. In one embodiment, a first package is installed on the carrier assembly and coupled with the protective shroud to form a pre-engagement assembly, the pre-engagement assembly is then engaged with a second package mounted on a printed circuit board.

Abstract: A scan test architecture includes first and second serial scan paths for transferring test data to and from an integrated circuit's logic. A first clock controls transfer of information on the first scan path and a second clock controls transfer of data on the second scan path. The first and second clocks are alternately enabled by a control signal initiated under program control of the external test system.

Abstract: A coprocessor 18 comprises a bus controller 24 which further comprises a primary bus controller 28 and a secondary bus controller 30 that drive a floating point processor core 26. The primary bus controller 28 comprises a memory mapped bus interface 32 for processing memory mapped format instructions and an I/O bus interface 34 for processing conventional I/O format instructions. The primary bus controller 28 remains essentially transparent for execution of I/O format instructions and translates memory mapped format instructions into sequential bus cycles compatible to an I/O bus interface for processing conventional I/O format instructions, and for execution by the floating point processor core.

Abstract: A data compression/decompression processor (a single-chip VLSI data compression/decompression engine) for use in applications including but not limited to data storage and communications. The processor is highly versatile such that it can be used on a host bus or housed in host adapters, so that all devices such as magnetic disks, tape drives, optical drives and the like connected to it can have substantial expanded capacity and/or higher data transfer rate. The processor employs an advanced adaptive data compression algorithm with string-matching and link-list techniques so that it is completely adaptive, and a dictionary is constructed on the fly. No prior knowledge of the statistics of the characters in the data is needed. During decompression, the dictionary is reconstructed at the same time as the decoding occurs. The compression converges very quickly and the compression ratio approaches the theoretical limit. The processor is also insensitive to error propagation.

Abstract: Test circuitry for a counter of n number of bits is described. The circuitry includes that which divides the counter into s number of segments when the counter is being tested in a test mode. The invention also includes circuitry for detecting when each segment nears the last count and overriding test mode to reenable a between-segment clock path between the segments before the last count to permit the last count to ripple through the counter to test connections between the segments on the next clock cycle. Previous test implementations did not test the interface between segments because of the prohibitive cost in tester time. In one embodiment, assuming equal numbers of b bits per segment, to fully test a counter using previous techniques, 2.sup.(n-b) +2.sup.b clock cycles would be required. In this technique, only (s-2)+2.sup.b clock cycles are required.

Abstract: Rotate circuitry operable to perform rotate operations on various size operands including preconditioning circuitry (10) for duplicating an operand a predetermined number of times to form a preconditioned word. The rotate operation is performed by shifter (22) which shifts the preconditioned word by a specified number of bits. For rotate through carry operations, Cy bit of the carry flag is inserted in the preconditioned word prior to shifting.

Abstract: A microprocessor has a plurality of input/output pins and processing coupled to the input/output pins. Circuitry is provided for selectively decoupling the processing circuitry with one or more of the input/output pins such that pins associated with enhanced features may be decoupled to provide compatibility with a desired microprocessor architecture.

Abstract: An integrated circuit, such as a microprocessor or math coprocessor, having a clock generator circuit for generating a high frequency internal clock signal based on an external input signal is disclosed. A clock generator circuit comprises circuitry for detecting an active edge of an input signal, circuitry for generating a plurality of clock edges responsive to the detection of the clock signal and circuitry for inhibiting the edge generating circuitry after generation of a predetermined number of clock edges. The factor by which the input clock signal is multiplied may be set by the circuit designer, or programmably set, without impact on the circuit design. Hence, a single circuit may be used to generate clocks of various frequencies. Further, the duty cycle of the generated clock is independent of the input clock signal.

Abstract: An integrated circuit, such as a microprocessor or math co-processor, having a clock generator circuit for generating a high frequency internal clock signal based on an external input clock signal is disclosed. The clock generator circuit includes a programmable delay stage having fixed and variable portions. The fixed portion preferably includes a series of logic elements of various types (NOR, NAND, NOT, pass gates, etc.), selected to match the worst case clock phase delay and which match speed variations as a function of voltage, temperature or processing conditions. The variable portion of the delay stage selects a propagation delay by way of programmable elements (e.g., mask programmable); multiplexers may be included therein to allow selection of the delay in a test mode.

Abstract: A carry skip adder uses independent paths for propagating a skip carry bit and a carry-in bit. Propagation of the carry-in bit is inhibited during a first portion of the clock cycle to prevent spurious carry-in signals from affecting the operation. During this period, other logic functions may be performed, including calculation of the propagation bits and generate bits for each adder block.

Abstract: A component carrier and mating system is disclosed for aligning and mating closely spaced leads of integrated circuit (IC) packages, which protects the integrated circuit packages and permits easy installation. The system is particularly adapted for aligning and mating integrated circuits which have high pin counts. A carrier assembly aligns for mating and interconnecting at least two integrated circuit packages having a plurality of leads extending from the packages. A protective shroud covers the stacked packages to maintain the packages in electrical and mechanical engagement and to assure that no damage occurs to the integrated circuit packages. In one embodiment, a first package is installed on the carrier assembly and coupled with the protective shroud to form a pre-engagement assembly, the pre-engagement assembly is then engaged with a second package mounted on a printed circuit board.

Abstract: A method and apparatus for performing division is described which first comprises approximating the short reciprocal of the divisor. A reciprocal bias adjustment factor is added to the approximation and the correctly biased short reciprocal is multiplied by a predetermined number of the most significant bits of the dividend and the product is truncated to generate a first quotient digit value. The multiplication takes place in a multiplier array having a rectangular aspect ratio with the long side having a number of bits at least as large as the number of bits required for the divisor. The short side of the multiplier array has a number of bits slightly greater by several guard bits than the number of bits required for a single quotient digit value, which is also determined to be the number of bits in the short reciprocal. The quotient digit value is multiplied by the full divisor and the exact product is subtracted from the dividend to yield an exact partial remainder.

Abstract: A multiplier system 12 is disclosed which provides for the negation of an operand stored in an operand register 14. When a negative operand must be loaded into a partial product generator 26, a carry bit is selectively generated in carry logic 44 and a selected bit or bits within the partial product is set to zero. During a subsequent pass through the multiplier system 12, a bit is added at a block 46 to provide for the addition of the required quantity for the negation of the operand.

Abstract: A variable bandwidth phase-locked loop clock generator circuit is disclosed. The PLL circuit includes a phase comparator which presents pump-up and pump-down signals, indicating the polarity of the desired frequency change. The phase comparator also generates multiple level control outputs to control the rate of the frequency change. A current source includes a reference leg having a plurality of resistors which are shorted out according to the control outputs, from which a bias signal is generated. The level of the bias signal controls current sources in the output leg of the current source to control the rate of change of the voltage applied to the voltage controlled oscillator. In addition, the bias signal also controls the slew rate of an active low-pass filter according to the desired response characteristic; the output of the filter is applied to the voltage controlled oscillator for generating the output clock signal.

Abstract: A rectangular array signed digit multiplier circuit 10 is disclosed which comprises a multiplier core (28). The circuit (10) comprises a C-latch (14), a D-latch (18), and A-latch (26), and a feedback latch (52) operable to store operands to be input into the multiplier core (28) through a MULTIPLIER INPUT, a multiplicand INPUT, an ADDER INPUT and a FEEDBACK INPUT, respectively. The product output by the multiplier core (28) may comprise the sum of the product of the values input through the MULTIPLIER INPUT and MULTIPLICAND INPUT and the ADDER and FEEDBACK INPUTS. The product is stored in a result latch (40) and may be used in subsequent passes through multiplier core (28) through the use of a data path coupling result latch (40) with feedback latch (52). Multiplier core (28) comprises a series connection of a times three adder level (56), a Booth recoder level (58), a partial product generator level (60), a level one adder level (62), a level two adder level (64) and a level three adder level (66).

Abstract: A bus precharge circuit is provided that precharges a bus line or node as an inverse function of the precharge level already attained on the bus line, such that the precharge level on the bus line is gradually approached. The precharge circuit charges the bus line to a midpoint between high and low logic states. The preexisting state of the bus line is stored and is used to select one of two voltage supplies to which the bus line may be partially pulled up or down. The switchpoint of a precharge circuit sensing gate is set to be equivalent to the switchpoint of the receiving gate of receiver on the bus line.

Abstract: A method and apparatus for performing the square root function which first comprises approximating the short reciprocal of the square root of the operand. A reciprocal bias adjustment factor is added to the approximation and the result truncated to form a correctly biased short reciprocal. The short reciprocal is then multiplied by a predetermined number of the most significant bits of the operand and the product is appropriately truncated to generate a first root digit value. The multiplication takes place in a multiplier array having a rectangular aspect raio with the long side having a number of bits essentially as large as the number of bits required for the desired full precision root. The short side of the multiplier array has a number of bits slightly greater by several guard bits than the number of bits required for a single root digit value, which is also determined to be the number of bits in the short reciprocal.

Abstract: A normalization circuit (24) which comprises a signed digit subtracter (25) coupled to operand registers (14, 19). The signed digit subtracter (25) subtracts the operands and inputs a signed digit difference to a pseudovalue converter (27). The pseudovalue converter (27) generates a pseudovalue in non-redundant format which contains its most significant non-zero bit in the selected bit position. The pseudovalue is output to a leading zero counter (28) which counts the number of leading zeroes in the pseudovalue.

Abstract: A rectangular array signed digit multiplier circuit (10) is disclosed which comprises a multiplier core (28). The circuit (10) comprises a C-latch (14), a D-latch (18), an A-latch (26), and a feedback latch (52) operable to store operands to be input into the multiplier core (28) through a MULTIPLIER INPUT, a multiplicand INPUT, and ADDER INPUT and a FEEDBACK INPUT, respectively, The product output by the multiplier core (28) may comprise the sum of the product of the values input through the MULTIPLIER INPUT and MULTIPLICAND INPUT and the ADDER and FEEDBACK INPUTS. The product is stored in a result latch (40) and may be used in subsequent passes through multiplier core (28) through the use of a data path coupling result latch (40) with feedback latch (52). Multiplier core (28) comprises a series connection of a times three adder level (56), a Booth recoder level (58), a partial product generator level (60), a level one adder level (62), a level two adder level (64) and a level three adder level (66).

Abstract: A method and apparatus for performing the square root function which first comprises approximating the short reciprocal of the square root of the operand. A reciprocal bias adjustment factor is added to the approximation and the result truncated to form a correctly biased short reciprocal. The short reciprocal is then multiplied by a predetermined number of the most significant bits of the operand and the product is appropriately truncated to generate a first root digit value. The multiplication takes place in a multiplier array having a rectangular aspect ratio with the long side having a number of bits essentially as large as the number of bits required for the desired full precision root. The short side of the multiplier array has a number of bits slightly greater by several guard bits than the number of bits required for a single root digit value, which is also determined to be the number of bits in the short reciprocal.