Patents Assigned to Dallas Semiconductor Corp.
  • Patent number: 6122704
    Abstract: Coin-shaped one-wire communication modules with a flange for mounting convenience may be attached to contact extensions on items such as work totes for ease of communication. A host computer can keep track and locate multiple items which have mounted communication modules with use of a single data line and a single ground line for all of the modules.
    Type: Grant
    Filed: March 14, 1995
    Date of Patent: September 19, 2000
    Assignee: Dallas Semiconductor Corp.
    Inventors: Steven N. Hass, Michael L. Bolan
  • Patent number: 6016255
    Abstract: Coin-shaped one-wire communication modules with a flange for mounting convenience may be attached to contact extensions on items such as work totes for ease of communication. A host computer can keep track and locate multiple items which have mounted communication modules with use of a single data line and a single ground line for all of the modules.
    Type: Grant
    Filed: March 15, 1993
    Date of Patent: January 18, 2000
    Assignee: Dallas Semiconductor Corp.
    Inventors: Michael L. Bolan, Nicholas M. G. Fekete
  • Patent number: 6005424
    Abstract: An integrated dynamic interconnect device for connecting and disconnecting at least a portion of a parasitically powered integrated electronic circuit, includes a power input, a power output, a signal input to receive a connect/disconnect signal, and an integrated switching mechanism which is responsive to the signal input receiving a connect/disconnect signal to electrically connect and disconnect the power input and the power output.
    Type: Grant
    Filed: December 28, 1995
    Date of Patent: December 21, 1999
    Assignee: Dallas Semiconductor Corp
    Inventor: James M. Douglass
  • Patent number: 5959926
    Abstract: A programmable power controller controls power between a primary power source and a secondary power source and powering first circuitry. The primary power source has a first voltage and the secondary power source has a second voltage. A control register has a first field, which is field used to activate circuitry used to direct power from the primary power source to the secondary power source. First logic circuitry compares the first voltage and the second voltage to determine which is greater and then couples the primary power source or the secondary power source, depending upon which is greater, to power the first logic circuitry, second logic circuitry, and memory. The memory is coupled to the first logic circuitry and is read and written to via an input/output buffer.
    Type: Grant
    Filed: April 13, 1998
    Date of Patent: September 28, 1999
    Assignee: Dallas Semiconductor Corp.
    Inventors: Brian W. Jones, Alan Mark Morton
  • Patent number: 5923159
    Abstract: A digital potentiometer capable of being connected directly to an electronic switch is disclosed. The digital potentiometer for example may utilize a 64 step resistor array, which would then have 64 steps. Each of the steps have precise values so as to accurately attenuate a signal in logarithmic steps. The logarithmic resistor is connected to a gate device which in turn has a voltage source connected to it designed to provide the threshold or turn-on voltage for the device for each of the 64 steps and wiper points of the resistor array.
    Type: Grant
    Filed: March 11, 1997
    Date of Patent: July 13, 1999
    Assignee: Dallas Semiconductor Corp.
    Inventor: Richard William Ezell
  • Patent number: 5913181
    Abstract: A comparator which for example can be used for a digital potentiometer is shown. Specifically, a dual differential input circuit with a push/pull amplifier at the output stage is disclosed wherein a crossing is detected in an inputted signal as the crossing occurs and wherein the push/pull amplifier pair at the output stage provides very fast detection of a crossing. This is particularly useful in acting as a trigger mechanism for changes in a digital potentiometer for example to elements noise caused as "wiper changes" occur.
    Type: Grant
    Filed: June 30, 1995
    Date of Patent: June 15, 1999
    Assignee: Dallas Semiconductor Corp.
    Inventor: Richard William Ezell
  • Patent number: 5912548
    Abstract: An electronic device for monitoring the operating conditions of a rechargeable battery, and includes a temperature monitor for monitoring the operating temperature of the rechargeable battery; a voltage determiner coupled to the rechargeable battery for measuring the potential level of the rechargeable battery; a one wire interface for outputting the information corresponding to the potential level of the rechargeable battery and the information corresponding to the temperature monitored by the temperature monitor; and a power regulator coupled to the rechargeable battery for supplying regulated power from the rechargeable battery to the temperature monitor and the voltage determiner. The voltage determiner includes an analog to digital converter and utilizes a successive approximation technique to determine and output a digital value corresponding to the potential level of the rechargeable battery.
    Type: Grant
    Filed: April 9, 1998
    Date of Patent: June 15, 1999
    Assignee: Dallas Semiconductor Corp.
    Inventors: Richard E. Downs, Robert Mounger
  • Patent number: 5828240
    Abstract: The present invention overcomes the shortcomings and deficiencies of the prior art by providing a circuit for processing an AC signal having a peak to peak envelope associated therewith, this circuit including structure for detecting the upper edge of the peak to peak envelope of the AC signal, structure for detecting the lower edge of the peak to peak envelope of the AC signal, structure for sampling the AC signal at a mid range upper point, and structure for sampling the AC signal at a mid range lower point.
    Type: Grant
    Filed: May 5, 1997
    Date of Patent: October 27, 1998
    Assignee: Dallas Semiconductor Corp.
    Inventor: Michael D. Smith
  • Patent number: 5821619
    Abstract: The replaceable power module includes a power section positioned between a cover and a frame. The cover is provided with clips to permit the attachment and detachment of the cover to the base as well the attachment and detachment of the power module to a surface mounted integrated circuit. The frame is provided with an opening for receiving the integrated circuit, and electrical contacts for electrically connecting the power module to the leads of an integrated circuit. The power section is electrically coupled to the frame and includes a battery and a crystal oscillator for controlling the integrated circuit.
    Type: Grant
    Filed: December 7, 1995
    Date of Patent: October 13, 1998
    Assignee: Dallas Semiconductor Corp.
    Inventors: Mark A. Gerber, Michael K. Strittmatter, Neil McLellan, Joseph P. Hundt
  • Patent number: 5812005
    Abstract: A circuit and associated method for determining the offset bias of a comparator by first shorting together the inputs of the comparator to apply the same voltage signal at each of the inputs of the comparator. The voltage signal at one of the inputs is then offset a select amount by applying varying selected resistances from a variable resistor to the comparator. The variable resistor is controlled by a programmable controller that is responsive to an input clock signal. At each selected amount of offset applied to the input, the output is monitored to determine if the output of the comparator has flipped, or changed state. When the output flips, the corresponding resistance setting is used to compensate for the corresponding offset bias of the comparator.
    Type: Grant
    Filed: July 30, 1996
    Date of Patent: September 22, 1998
    Assignee: Dallas Semiconductor Corp.
    Inventors: William Richard Ezell, Robert Mounger
  • Patent number: 5801411
    Abstract: An integrated capacitor structure having substantially reduced temperature and voltage coefficients including a combination of conventional N-depletion and P-depletion MOS gate capacitors connected in parallel and optimized for use at low bias voltages, where both the N-depletion and P-depletion capacitor structures have substantially zero temperature coefficients in their fully depleted region of operation.
    Type: Grant
    Filed: January 11, 1996
    Date of Patent: September 1, 1998
    Assignee: Dallas Semiconductor Corp.
    Inventor: Kevin Mark Klughart
  • Patent number: 5798669
    Abstract: An integrated voltage/current reference having substantially reduced temperature and voltage coefficient with simultaneous nanowatt power consumption includes a nanopower voltage/current reference topology having a substantial temperature coefficient and minimal voltage coefficient and augmented with a floating voltage proportional to absolute temperature (PTAT) within a feedback loop to compensate for differentials in .beta. exponential temperature dependencies of N-Channel and P-Channel MOS devices used within commonly available semiconductor processes. The resulting reference supplies both voltage as well as current references which have greatly reduced temperature coefficients. In addition, the resulting circuit topology generates a voltage reference which has a parabolic temperature coefficient similar to that produced by a conventional bandgap reference.
    Type: Grant
    Filed: July 11, 1996
    Date of Patent: August 25, 1998
    Assignee: Dallas Semiconductor Corp.
    Inventor: Kevin Mark Klughart
  • Patent number: 5784624
    Abstract: An arbitrator for selectively permitting access to a common resource by a priority device and two non-priority devices, includes a priority request reception device for receiving a priority request to access the resource by the priority device; two second request reception devices for receiving non-priority requests to access the resource by the two non-priority devices; a prioritizer coupled to receive indications of times when the priority request reception device receives the priority request and when the two non-priority request reception devices receive the non-priority requests, with the prioritizer permitting access to the resource by the priority device and non-priority device in a predetermined order.
    Type: Grant
    Filed: January 31, 1996
    Date of Patent: July 21, 1998
    Assignee: Dallas Semiconductor Corp
    Inventors: James M. Douglass, Dallas L. Ledlow
  • Patent number: 5759049
    Abstract: A connector for electrically connecting a first conductor on a top surface of a first substrate with a second conductor on a top surface of a second substrate, when the second substrate is positioned beneath the first substrate, the connector includes an electrically conductive clip having a first prong and a second prong, with at least a portion each of the first and second prongs positionable at the top and bottom surfaces of the first substrate respectively, such that the first and second prongs provide a clipping force upon the first substrate to engage the first substrate with the clip. The connector further includes a first electrically conductive contact affixed to the first prong of the clip and is for contacting the first conductor when the clip engages the first substrate. An electrically conductive third prong is connected and extends from the clip, and includes a third electrically conductive contact affixed to the third prong for contacting the second conductor.
    Type: Grant
    Filed: May 15, 1996
    Date of Patent: June 2, 1998
    Assignee: Dallas Semiconductor Corp.
    Inventor: Mark A. Gerber
  • Patent number: 5758060
    Abstract: A hardware circuit for verifying the execution of software is disclosed wherein the circuit compares a stored value with another value that is stored at at least one predetermined time in the course of program execution. If the two values correspond in some predetermined fashion then it is verified with a level of certainty that the program executed the program steps at or near the predetermined times.
    Type: Grant
    Filed: March 5, 1996
    Date of Patent: May 26, 1998
    Assignee: Dallas Semiconductor Corp
    Inventors: Wendell L. Little, Matthew K. Adams, David A. Bunsey, Jr.
  • Patent number: 5686863
    Abstract: An equalizer, for providing a tunable pole/zero compensated output signal, includes a integrated tone control circuit with a MOSFET-C configuration such that the spacing between the pole and the zero and the center frequency of the pole/zero pair can be tuned by varying the resistance of MOSFET resistors using variable voltage sources applied to the gates of the MOSFETs.
    Type: Grant
    Filed: September 29, 1995
    Date of Patent: November 11, 1997
    Assignee: Dallas Semiconductor Corp.
    Inventor: Frank A. Whiteside
  • Patent number: 5684828
    Abstract: A wireless-accessible module which provides first and second wireless-transmitter control signals, such that the first transmitter control signal can be activated automatically, in response to incoming wireless signals, but the second transmitter control signal can only be activated by manual input or direct command. Preferably the two control signal outputs are used to select the power level of transmission on a single predetermined frequency; but alternatively these outputs may be used to control two different RF transmitters and/or two different antennas.
    Type: Grant
    Filed: October 10, 1995
    Date of Patent: November 4, 1997
    Assignee: Dallas Semiconductor Corp.
    Inventors: Michael L. Bolan, Donald R. Dias, William Lee Payne, II
  • Patent number: 5682068
    Abstract: The power cap includes a power supply positioned between a cover and a base. The cover is provided with clips to permit the attachment and detachment of the cover to the power supply and the base. The base is provided with surface mounted NRTC or NVSRAM chips and electrical contacts. The power supply is provided with a crystal oscillator and a battery for controlling the operation of the NRTC or NVSRAM chips, and spring contacts for maintaining the electrical connection between the base and the power supply.
    Type: Grant
    Filed: December 7, 1995
    Date of Patent: October 28, 1997
    Assignee: Dallas Semiconductor Corp.
    Inventors: Neil McLellan, Mark A. Gerber, Michael K. Strittmatter, Joseph P. Hundt
  • Patent number: 5644605
    Abstract: Jitter attenuators (100) with a phase detector (104) to control a crystal oscillator to remove jitter wherein the phase detector includes both a sequential phase/frequency detector (200) of low transistor count and an arrangement of two sequential phase/frequency detectors (198 and 200) to increase gain and two drivers for the crystal oscillator.
    Type: Grant
    Filed: June 27, 1995
    Date of Patent: July 1, 1997
    Assignee: Dallas Semiconductor Corp.
    Inventor: Frank A. Whiteside
  • Patent number: D383438
    Type: Grant
    Filed: March 6, 1996
    Date of Patent: September 9, 1997
    Assignee: Dallas Semiconductor Corp.
    Inventors: Mark A. Gerber, Michael K. Strittmatter