Abstract: An integrated circuit terminator for a SCSI bus with resistors made of laser-blowable fuses in an array and a reference voltage source made with a bandgap generator and a two stage amplifier including a dummy isolation stage for providing symmetrical mismatch currents.

Abstract: A fastener and corresponding communication system comprises a first fastener having a first end and a second fastener having a second end. The first fastener has an integrated circuit positioned to be electrically coupled to a first communication interface on the first end of the fastener. The second end also has a second communication interface, the first communication interface and the second communication interface electrically coupled together when the first fastener and the second fastener are fastened together. The first fastener preferably has a hollow cavity therethrough and the integrated circuit is positioned inside the first fastener. At least one electrical signal line, preferably only one, exists through the hollow cavity in communication with the integrated circuit.

Abstract: An integrated circuit memory which includes at least some RAM/ROM hybrid columns. The RAM/ROM hybrid cells operate as normal SRAM cells forever, unless and until they are programmed to operate as ROM cells. Thus users who need the extra security permitted by ROM encoding can have this capability, while users who do not need ROM encoding can use off-the-shelf parts as RAM only.

Abstract: A method and apparatus for performing finite impulse response filtering in real time is accomplished by taking advantage of symmetrical FIR coefficients of FIR filters in audio equipment. Due to the symmetry of the coefficients, each coefficient, other than the T0 coefficient, has an almost identical counterpart. Thus, only one of the identical coefficient needs to be stored and is used in conjunction with two data points. The two data points are summed together prior to multiplication by the corresponding coefficient to produce an accumulated resultant. This process repeats for each pair of data points, and corresponding FIR coefficient, until a final resultant is obtained.

Abstract: A method and apparatus for a controlled oscillator which may be incorporated in a phase locked loop is accomplished by including a current controlled reference, a current mirror and a plurality of inverters that form a ring oscillator within the controlled oscillator. The controlled reference provides a current control signal to the current mirror, which, in turn, provides a load control signal to each inverter of the ring oscillator. Each inverter is characterized by a differential load section which includes a pair of load transistors for receiving the load control signal and for providing a current source from the load control signal and a pair of clamping transistors configured to provide a non-linear clamping circuit which limits the voltage range of a differential output. The load transistors are connected in parallel with the clamping transistors to provide a linear differential output.

Abstract: A histogram generator system uses a sensor to periodically sample a value of a physical variable to produce at least one sample of the physical variable and a selector allocate each sample of the value of the physical variable into a corresponding counter of a counter array. The counter accumulates a number of occurrences of the value of the sample(s) of the physical variables.

Abstract: A nonvolatile memory, includes multiple nonvolatile registers with each nonvolatile register including memory cells, and further includes circuitry that writes information to each of the nonvolatile registers one at a time, in a rotating order to prolong the prevention of tunneling oxide breakdown.

Abstract: A dynamic bias stabilization device providing significant control of the operating point and frequency stability of a low-power crystal oscillator includes an inverting CMOS amplifier as its primary gain element and a filtered resistive current source to supply the inverting amplifier with operating power. A number of MOS transmission gates and integrated capacitors configured in a T-type network are used as the amplifier feedback element. The control voltages for these feedback transmission gates are derived from the current source which also supplies power to the crystal oscillator amplifier.

Abstract: A communication system providing read and write access to analog and digitally controlled calibration and configuration information contained within prepackaged crystal oscillators having a crystal oscillator electrical interface with power (VCC), ground (GND), output enable (OE), and oscillator output (XO) interface pins. An output enable (OE) signal is used to control the activity state of the crystal oscillator output, with a pullup MOSFET connected to the XO pin to detect a logic low level at the XO pin during times when the OE signal is logically inactive. A state machine controls access to a serial shift register having multiple calibration and configuration bits. The calibration and configuration bits are used in performing an oscillator specific calibration and configuration function. The state machine also controls the reads and writes of the calibration and configuration shift register.

Abstract: A dual storage cell memory includes an array of dual storage cells, each of the dual storage cells containing a first memory cell and a second memory cell. The first and second memory cells are well known six-transistor static memory cells with the addition of transfer circuitry for transferring data directly from the internal data nodes of each of the memory cells to its corresponding complementary memory cell without requiring the use of the enable transistors or the bit lines associated with each of the dual storage cells.

Abstract: A socket system that comprises a printed circuit board; an electrical module; and a socket having a hollow core. The socket holds the electrical module and is capable of electrically coupling the electrical module to the printed circuit board. The electrical module has at least one electrical lead. The socket has at least one electrical lead capable of electrically coupling with the electrical lead(s) of the electrical module. The electrical module comprises a second printed circuit board having a first and second surface; a lithium battery positioned on the first surface of the second printed circuit board and electrically coupled with the second printed circuit board, a crystal positioned on the first surface of said second printed circuit board and electrically coupled with the second printed circuit board, and an integrated circuit positioned on the second surface of the second printed circuit board.

Abstract: Preferred embodiments have an external RAM controlled by logic on an internal RAM with overlapping address space. Read requests from addresses in the overlapping portion are directed to internal RAM only by controlling the output enable signal of external RAM; contrarily, writes to addresses in the overlapping portion proceed in both internal and external RAM simultaneously.

Abstract: A dual storage cell memory includes an array of dual storage cells, each of the dual storage cells containing a first memory cell and a second memory cell. The first and second memory cells are well known six-transistor static memory cells with the addition of transfer circuitry for transferring data directly from the internal data nodes of each of the memory cells to its corresponding complementary memory cell without requiring the use of the enable transistors or the bit lines associated with each of the dual storage cells.

Abstract: An integrated circuit, in which some areas of the chip are powered from battery, but at least two other areas of the chip can draw power from independent on-chip power-storage capacitors (which are diode-isolated to accumulate charge from an external signal line). The signal line's input buffer draws power from one capacitor, and the decoder logic draws power from another. Thus, even if the first capacitor is depleted by the signal line's staying in the high-current regime, it will be powered up again when the signal line is again driven high; and the charge stored in the second capacitor will permit the decoding logic to operate. Preferably the second capacitor also powers circuitry which encodes a unique serial number for the chip. Thus, even after the battery has died, the chip can be interrogated to ascertain its unique serial number.

Abstract: A digital potentiometer, in which the three terminals of the potentiometer are all free-floating. The position of the wiper is selected by a control signal received on a serial port. A change is made in the effective position of the wiper until the reset-bar signal goes low. Thus, the value of the potentiometer can be directly changed to any desired value, without intermediate incrementing steps. Moreover, this control arrangement allows multiple such potentiometers to share the same serial control bus, in a "daisy chain" configuration. This has the advantage that all of the potentiometers on the serial control bus will change their values at the same time. (This is advantageous, for example, in systems where such potentiometers are used to set the gain characteristics of multiple op amps.

Abstract: A bidirectional voltage to current converter circuit with extended dynamic range includes a first and second operational amplifier in which the input voltage terminal is connected to the negative input of both operational amplifiers. The outputs of the operational amplifiers each directly drive the gates of two transistors which operate as a current mirror circuit. The current mirror transistors associated with the first operational amplifier are p-channel transistors with their sources connected to VDD, and the two transistors driven by the second operational amplifier are n-channel transistors with their sources connected to ground. The drains of the first p-channel transistor and the first n-channel transistor are coupled back to the positive inputs of the first and second operational amplifiers respectively; and also each drain is separately connected to one end of a resistor, the other ends of the two resistors are connected together and to a reference voltage.

Abstract: A low power timekeeping system utilizes a state machine to first read seconds stored in a RAM and update seconds and then determine if the minutes requires updating. If the minutes do not require updating then the sequencer stops operation until the next update cycle. Similarly, the minutes, hours, days of the week, date of the month, month, and year are updated only as needed in each update cycle thereby lowering the power requirement needed by the timekeeping system.

Abstract: A transceiver (100) for TTL and RS232 communication with automatic sensing (130) of the type of input and adjustment of the output to correspond together with current stealing (131) from the input communication lines to provide extreme voltages for transmission. Hysteresis and surge suppression are built into the sensing.

Abstract: A telephone network interface integrated circuit with digitally based loop current detection and digitally based ring signal detection. The ring signal detection includes discrimination with a cutoff frequency of about 13 Hz to distinguish ring signals from dialing signals. The discrimination includes filtration followed by triggering an oscillator for one time period and checking whether the number of oscillations exceeds a threshold.

Abstract: An integrated circuit containing two digital potentiometers with each potentiometer including a passive resistor string with tap points. Tap point selection is programmed through a three-wire serial port. An output multiplexing the selected tap points permits tying the two potentiometers in series to form a single potentiometer of twice the size.