Abstract: Methods, systems, and arrangements enable increased security for a processor, including by implementing block encryption. The block may include multiple instructions and/or operations to be executed by the processor. The block may also include multiple bytes that are read into the processor byte by byte. Once a block-wide encrypted buffer has been filled from an external memory source, the block may be decrypted using an encryption algorithm (e.g., the Data Encryption Standard (DES), the triple DES, etc.), and the decrypted block may be forwarded to a decrypted buffer. The decrypted block may thereafter be moved into a cache, which may optionally be organized into an equivalent block width (e.g., for each way of a multi-way cache). Therefore, when a processing core/instruction decoder needs a new instruction, it may retrieve one from the cache, directly from the decrypted buffer, or from external memory (e.g., after undergoing decryption).

Abstract: A security device is disclosed. In one embodiment, the security device includes a memory device comprising having a first memory portion configured to store a device ID; and a second memory portion configured to store a device secret. The security device further includes a processor connected to the memory device wherein the processor is configured to read the stored device ID from the first memory portion and the stored device secret from the second memory portion and perform a nonreversible computation using the stored device ID, the stored device secret, and a challenge as seeds. Additionally, the security device includes a communication circuit connected to the processor, the communication circuit configured to receive the challenge from a host device and to communicate a result of the nonreversible computation performed by the processor.

Abstract: A battery charger with charging parameter values derived from communication with a battery pack to be charged. Communication is over a one-wire bus with battery pack transmissions in response to charger inquiries. The battery charger may be in the form an integrated circuit driving a power transistor or other controllable DC supply. A battery pack may contain a program with multiple charging currents and charging interval termination methods such as time, temperature rise, and incremental voltage polarity. A lack of communication may be invoke a default charging program or denial of access to the charger. The charger also communicates over a high-speed three-wire bus with an external computer for analysis of identification information acquired from the battery and for control of the charger.

Abstract: Methods, systems, and arrangements enable efficient reprogramming of a memory block of a microcontroller. Two blocks of memory each have a different logical location with respect to a processor of the microcontroller. The first memory may store vector information to be executed by the processor. The second memory may store data information. The logical location of each memory block is dependent on the value of a pre-determined bit in a specified register. When a user wishes to reprogram the contents of the first memory, the user enters new code into the second memory. Upon completion, the value of the pre-determined bit is changed, and the logical locations of the first and second memories are interchanged. In effect, the newly entered code from the second memory is accessed as if it were in the first memory (e.g., from an addressing perspective), and the processor may execute the new program (e.g., after the processor undergoes a system reset).

Abstract: The present invention provides an 8-bit microcontroller capable of supporting expanded addressing capability in one of three address modes. The microcontroller operates in either the traditional 16-bit address mode, a 24-bit paged address mode or in a 24-bit contiguous address mode based on the setting of a new Address Control (ACON) Special Function Register (SFR). The 24-bit paged address mode is binary code compliant with traditional compilers for the standard 16-bit address range, but allows for up to 16M bytes of program memory and 16M bytes of data memory to be supported via a new Address Page (AP) SFR, a new first extended data pointer (DPX) SFR and a new second extended data pointer (DPX1) register. The 24-bit contiguous mode requires a 24-bit address compiler that supports contiguous program flow over the entire 24-bit address range via the addition of an operand and/or cycles to either basic instructions.

Abstract: A battery charger with charging parameter values derived from communication with a battery pack to be charged. Communication is over a one-wire bus with battery pack transmissions in response to charger inquiries. The battery charger may be in the form an integrated circuit driving a power transistor or other controllable DC supply. A battery pack may contain a program with multiple charging currents and charging interval termination methods such as time, temperature rise, and incremental voltage polarity. A lack of communication may be invoke a default charging program or denial of access to the charger. The charger also communicates over a high-speed three-wire bus with an external computer for analysis of identification information acquired from the battery and for control of the charger.

Abstract: A device and method for measuring temperature is disclosed. The device, for example, can include a thermocouple configured to generate a voltage indicative of a junction temperature; a memory device configured to store a unique device ID and to store data; a logic unit connected to the thermocouple and the memory device; an I/O interface connected to the logic unit, the I/O interface configured to communicate with a computer system; and an internal temperature sensor connected to the logic unit, the internal temperature sensor configured to determine a cold junction temperature.

Abstract: A battery power management system comprising a system processor, a fuel gauge algorithm running on the system processor, at least one battery fuel cell electrically connected to the system processor, a battery data collector electrically connected to the battery fuel cell, with the battery data collector collecting electrical power data from the battery fuel cell and transmitting the electrical power data to the fuel gauge algorithm, where said fuel gauge algorithm converts the electrical power data to active and standby battery power information.

Abstract: Methods, systems, and arrangements enable efficient reprogramming of a memory block of a microcontroller. Two blocks of memory each have a different logical location with respect to a processor of the microcontroller. The first memory may store vector information to be executed by the processor. The second memory may store data information. The logical location of each memory block is dependent on the value of a pre-determined bit in a specified register. When a user wishes to reprogram the contents of the first memory, the user enters new code into the second memory. Upon completion, the value of the pre-determined bit is changed, and the logical locations of the first and second memories are interchanged. In effect, the newly entered code from the second memory is accessed as if it were in the first memory (e.g., from an addressing perspective), and the processor may execute the new program (e.g., after the processor undergoes a system reset).

Abstract: An improved random number generator for micro-controllers is provided with multiple free running oscillators. These oscillators may be ring oscillators. They run at different frequencies. A phase difference between at least two of the oscillators provides the random number. The determination of a phase difference can be done by sampling the high speed oscillator using the lower speed oscillator. This sampling of the oscillators for the determination of a phase difference can be controlled by an oscillators as well. The random number is picked up from a shift register which provides feedback to a control circuit which can alter the frequency of one or more (including all) of the oscillators so that an increased randomness can be achieved. The random number from the shift register is loaded into a linear feedback shift register (LFSR) to generate independent uniform random data.

Abstract: A temperature compensated crystal oscillation circuit adapted to be contained within a small device package and providing an output frequency accuracy of approximately +/−2 ppm over a temperature range or less than 2 minutes per year over the temperature range. The device includes crystal and a single integrated circuit wherein the integrated circuit has a temperature sensing circuit with a digital output, control circuitry, a memory circuit and a switched capacitor array for compensating the oscillation of the crystal oscillator over temperature.

Abstract: A device and method to regulate an electronic device in response to temperature changes is shown and described. For example, the present invention can control devices that are operable in different operational modes. The method and the device can be used so as to include steps of sensing a temperature; accessing a table using the sensed temperature; reading an operational mode indicator from the table, wherein the operational mode indicator corresponds to the sensed temperature; and operating the device in the proper one of the operational modes that corresponds to the operational mode indicator.

Abstract: A battery charger with charging parameter values derived from communication with a battery pack to be charged. Communication is over a one-wire bus with battery pack transmissions in response to charger inquiries. The battery charger may be in the form an integrated circuit driving a power transistor or other controllable DC supply. A battery pack may contain a program with multiple charging currents and charging interval termination methods such as time, temperature rise, and incremental voltage polarity. A lack of communication may be invoke a default charging program or denial of access to the charger. The charger also communicates over a high-speed three-wire bus with an external computer for analysis of identification information acquired from the battery and for control of the charger.

Abstract: A device and method for measuring temperature is disclosed. The device, for example, can include a thermocouple configured to generate a voltage indicative of a junction temperature; a memory device configured to store a unique device ID and to store data; a logic unit connected to the thermocouple and the memory device; an I/O interface connected to the logic unit, the I/O interface configured to communicate with a computer system; and an internal temperature sensor connected to the logic unit, the internal temperature sensor configured to determine a cold junction temperature.

Abstract: A system and methods for controlling power flow between a first and a second power supplies and an appliance. A first switch is coupled to the first power supply for switching power flow between the first power supply and the appliance. A second switch is coupled to the second power supply for switching power flow between the second power supply and the appliance. A first controller circuit is coupled to the first switch and the first power supply for monitoring at least one parameter of the first power supply and actuating the first switch to cease power flow if the at least one monitored parameter exceeds a given value, or deviates from a range of values. A second controller circuit is coupled to the first controller circuit, the second switch, and the second power supply for monitoring at least one parameter of the second power supply and actuating the second switch to cease power flow if the at least one monitored parameter exceeds a give value, or deviates from a given range.

Abstract: A temperature compensated crystal oscillation circuit adapted to be contained within a small device package and providing an output frequency accuracy of approximately +/−2 ppm over a temperature range or less than 2 minutes per year over the temperature range. The device includes crystal and a single integrated circuit wherein the integrated circuit has a temperature sensing circuit with a digital output, control circuitry, a memory circuit and a switched capacitor array for compensating the oscillation of the crystal oscillator over temperature.

Abstract: An electronic module having at least a microprocessor and co-processor on a single integrated circuit. The electronic module can be contained in a small housing. The electronic module provides secure bidirectional data communication via a data bus. The electronic module may include an integrated circuit comprising a microprocessor, and a co-processor adapted to handle 1,024-bit modulo mathematics primarily aimed at RSA calculations. The electronic module is preferably contained in a small token sized metallic container and will preferably communicate via a single wire data bus which uses a one-wire protocol.

Abstract: An initializer that responds to change in a power supply potential level, for generating an initialize signal to initialize a circuit to a select state, the initializer includes a power-on reset circuit that switches between an active and a powered-down state, and is for generating the initialize signal. The initializer also includes a wake-up circuit that monitors the power supply potential level and switches the power-on reset circuit from the powered-down state to the active state when selected change in the power supply potential level occurs.

Abstract: An apparatus for monitoring the condition of a battery. The apparatus includes a battery clip that is used to secure a battery to a battery connection and a battery monitoring IC. The battery monitoring IC takes a “load vs. no-load measurement” and the results are recorded in a register. When the battery reaches a certain low voltage state, register bits are set and an output is generated. Furthermore, the exemplary embodiment includes a removal detection circuit for detecting removal and replacement of the battery and for preventing voltage floating on the battery output line.