Abstract: A method of capturing a color image includes steps of operating a first sensor of a camera to integrate a first charge over a first time interval, operating a second sensor of the camera to integrate a second charge over a second time interval and scanning the first and second sensors to readout the respective first and second charges during a third time interval. The first time interval overlaps the second time interval. The third time interval includes no overlapping time with the first time interval. The third time interval includes no overlapping time with the second time interval.

Abstract: A sensor includes control circuitry and a pixel. The pixel includes a photo site, a first storage node and a second storage node. The control circuitry causes the pixel to transfer a first collected signal from the photo site to the first storage node during a first period, to transfer a second collected signal from the photo site to the second storage node during a second period that follows the first period, and to transfer the first and second collected signals out of the pixel during a third period that follows the second period.

Abstract: An active gate includes a substrate of a first conductivity type, a channel of a second conductivity type formed in the substrate, a first gate region of the first conductivity type formed in a corresponding first portion of the channel, and a first contact connected to the first gate region. The first gate region covers a first area, and the first contact covers a fraction of the first area. A pixel or register element includes an active gate, a second gate region of the first conductivity type formed in a corresponding second portion of the channel, and a second contact connected to the second gate region. The second gate region covers a second area and is spaced by a first gap from the first gate region. The second contact covers a fraction of the second area. The pixel or register element further includes a first gate electrode insulatively spaced from and disposed over the first gap.

Abstract: A TDI sensor includes a first readout register and a plurality of sensor columns. The first readout register includes a plurality of first readout register elements. A first sensor column includes a photogate and a diode photodetector at an end. The diode photodetector is either a photodiode or a pinned photodiode. The photogate is coupled through the diode photodetector and from there through a transfer gate to a corresponding readout register element.

Abstract: A method of capturing a color image includes steps of operating a first sensor of a camera to integrate a first charge over a first time interval, operating a second sensor of the camera to integrate a second charge over a second time interval and scanning the first and second sensors to readout the respective first and second charges during a third time interval. The first time interval overlaps the second time interval. The third time interval includes no overlapping time with the first time interval. The third time interval includes no overlapping time with the second time interval.

Abstract: A camera includes a first sensor disposed to image light that propagates along a reflected axis, a second sensor disposed to image light that propagates along a direct axis, and a rotatable structure disposed to define a rotation plane that is oblique to both the reflected axis and the direct axis. The rotatable structure includes either a first transmission sector, a first reflection sector disposed adjacent to the first transmission sector, a second transmission sector disposed adjacent to the first reflection sector and a second reflection sector disposed adjacent to the second transmission sector or the rotatable structure includes a first reflection sector, a first opaque sector disposed adjacent to the first reflection sector, and a first transmission sector disposed adjacent to the first opaque sector.

Abstract: A sensor includes an array of pixels organized in rows and columns and a plurality of metal busses overlaying the array of pixels. A first column of pixels includes a proximal set of first pixels and a distal set of first pixels separated by a first jog region. A second column of pixels includes a proximal set of second pixels and a distal set of second pixels separated by a second jog region. The first jog region is displaced in a column direction and in a lateral direction transverse to the column direction from the second jog region. A first metal bus is insulatively disposed over both the first and second jog regions.

Abstract: A circuit includes a circuit chip and a plurality of clock drivers external to the circuit chip. The circuit chip includes a plurality of isolated clocking subunits and a corresponding plurality of terminals. Each clocking subunit is electrically isolated from any other clocking subunit. Each clocking subunit is coupled to a respective terminal. For each of the plurality of terminals, an output from one and only one clock driver of the plurality of clock drivers is coupled to the corresponding terminal of the plurality of terminals, and inputs of all clock drivers are coupled together.

Abstract: A pixel includes five transistors, a photodetector and a storage node. A first transistor is coupled between the photodetector and the storage node. A second transistor includes a second transistor source and a second transistor drain. The second transistor source is coupled to the storage node. The second transistor drain is coupled to an output drain voltage. A third transistor includes a third transistor drain. The third transistor is coupled between the photodetector and a pixel reset voltage. The third transistor drain is coupled to the pixel reset voltage. The pixel reset voltage is different than the output drain voltage.

Abstract: A method includes a first step followed by a second step. The first step includes transferring photo charges in a delay register into a first readout register, transferring photo charges in a first storage register into the delay register, and transferring photo charges in a second storage register into a second readout register. The second step includes collecting photo charges in the first storage register, collecting photo charges in the second storage register, shifting photo charges in the first readout register toward a first output, and shifting photo charges in the second readout register toward a second output.

Abstract: A column slice of a CMOS TDI sensor includes a column bus, a column of pixels, plural first switches, a column of accumulators, plural second switches, plural third switches and output bus 39. Each of the plural first switches is coupled between the column bus and a corresponding pixel of the column of pixels, and each of the plural second switches is coupled between the column bus and a corresponding accumulator of the column of accumulators. In operation, only one switch at a time of plural first switches is “on” to connect the voltage signal from a corresponding pixel to the column bus while all remaining plural first switches are “off” to isolate the column bus from all remaining pixels. Only one of the plural second switches is “on” to connect the signal on the column bus to an accumulator while all remaining plural second switches are “off” to isolate the bus from all remaining accumulators.

Abstract: An apparatus includes a sensor and a bundle of optical fibers. The bundle of optical fibers has a first end and a second end. The bundle of optical fibers at the first end extends in a first fiber direction and defines a first section plane that is normal to the first fiber direction. The first end defines a first end plane that is obliquely oriented with respect to the first section plane. The bundle of optical fibers at the second end extends in a second fiber direction and defines a second section plane that is normal to the second fiber direction. The second end defines a second end plane that is obliquely oriented with respect to the second section plane. The sensor is disposed in a confronting relation with the second end.

Abstract: An encoder includes a linear offset amplifier, a linear analog to digital converter coupled to the linear offset amplifier, a switched offset amplifier, a switched analog to digital converter coupled to the switched offset amplifier, and a video controller. The video controller is coupled to both the linear and switched analog to digital converters. The video controller is configured to set both gains and offsets of the linear and switched analog to digital converters so that the gain and offset of the linear analog to digital converter is different than the gain and offset of the switched analog to digital converter.

Abstract: A method of sensing radiation in a pixel includes applying a transfer clock signal, applying a pixel reset clock signal, and applying a pixel reset voltage. The applying a transfer clock signal applies the transfer clock signal to a gate electrode of a transfer gate transistor. The applying a pixel reset clock signal applies the pixel reset clock signal to a gate electrode of the pixel reset transistor. The applying a pixel reset voltage applies the pixel reset voltage to a drain of the pixel reset transistor. The method further includes switching the transfer clock signal to a high state, switching the pixel reset clock signal to a high state, switching the pixel reset voltage to a low state, switching the pixel reset voltage to a high state, and switching the pixel reset clock signal to a low state at a beginning of an integration cycle.

Abstract: A line scan sensor includes first and second rows of pixels, corresponding first and second readout registers, and a first clocking structure disposed between the first row of pixels and the first readout register. The first clocking structure includes a transfer gate electrode and a delay well electrode. In an alternative embodiment, a method includes a first step followed by a second step. The first step includes transferring photo charges in a delay register into a first readout register, transferring photo charges in a first storage register into the delay register, and transferring photo charges in a second storage register into the second readout register. The second step includes collecting photo charges in the first storage register, collecting photo charges in the second register, shifting photo charges in a first readout register toward a first out put, and shifting photo charges in a second readout register toward a second output.

Abstract: A sensor formed in a substrate of a first conductivity type in a first concentration to express a first intrinsic potential includes CMOS circuitry to control the sensor, a first well of the first conductivity type in a second concentration (greater than the first concentration) formed in the substrate to express a second intrinsic potential, and a photodiode region of a second conductivity type formed in the first well. The first and second intrinsic potentials induce a field between the substrate and the first well that repels photo generated charge from drifting from the substrate into the first well. Alternatively, a sensor formed in a substrate of a first conductivity type includes CMOS circuitry to control the sensor, a first well of a second conductivity type formed in the substrate, a second well of the first conductivity type formed in the first well, and a photodiode region of the second conductivity type formed in the second well.

Abstract: A TDI sensor includes a column of pixels ordered from an initial pixel to a final pixel where each pixel includes reticulated clock conductors arranged to define a reticulation area and a pixel charge handling capacity. The reticulation area of a pixel increases from the final pixel to the initial pixel, and the pixel charge handling capacity increases from the initial pixel to the final pixel. The sensor includes a first bus structure of polysilicon, where the bus structure includes register element sets and each register element set includes a plurality of clock conductors. Each register element set includes a corresponding pixel reticulation area, and the pixel reticulation area of a first register element set is unequal to a pixel reticulation area of another register element set. The sensor also includes a second bus structure of metal disposed substantially diagonally to the first bus structure. The second bus structure includes clock bus sets, and each clock bus set includes bus conductors.

Abstract: A circuit includes a programmable delay circuit to provide a sequence of delayed pulses, an A/D circuit to convert a sequence of values into digital values sampled at times defined by the sequence of delayed pulses, and a jitter correction circuit to adjust the programmable delay circuit based on a sequence of digital values from the A/D circuit sampled at times defined by the sequence of delayed pulses.

Abstract: A pixel includes five transistors, a pinned photodiode and a storage node. A first transistor is coupled between the pinned photodiode and the storage node. A second transistor is coupled between the storage node and an output drain voltage. A third transistor is coupled between the pinned photodiode and a pixel reset voltage. The pixel reset voltage is different than the output drain voltage.

Abstract: A single phase charge-couple device (CCD) transfer device in a substrate of a first conductivity type. The device includes a gated region and a photo-diode region. The gated region includes a gated part and a gate electrode insulatively spaced over the gated part. The photo-diode region includes first, second, and third diode sub-regions. The second diode sub-region is formed of a second conductivity type; the third diode sub-region is formed of the first conductivity type in the second diode sub-region; and the first diode sub-region is formed of the first conductivity type in the second diode sub-region. The first and third diode sub-regions contain different dopant concentrations. The gated part is either a buried channel gated part or a surface channel gated part. The buried channel gated part includes a channel of the second conductivity type and a first gated sub-region formed in the channel.