Abstract: The invention is directed to an induction coil which includes a flat spirally wound portion and a tubular spirally wound portion extending from the outer edge of the flat portion. The axis of the tubular portion is substantially perpendicular to the flat portion. The coil is useful in a plasma production apparatus which includes a chamber having walls and adapted to be evacuated. A window extends into the chamber from one of the walls. The coil is in the window with the flat portion being at the bottom of the window.

Abstract: An active matrix electroluminescent display (AMELD) having an improved light emitting efficiency and methods of operating the AMELD to produce gray scale operation comprises a plurality of pixels, each pixel including a first transistor having its gate connected to a select line, its source connected to a data line and its drain connected to the gate of a second transistor, the second transistor having its source connected to the data line and its drain connected to a first electrode of an electroluminescent (EL) cell. The EL cell's second electrode is connected to alternating high voltage means. A method for producing gray scale performance including the step of varying the length of time the second transistor is on while the alternating voltage is applied to the EL cell is also disclosed.

Abstract: An optical device having a substrate with a waveguide layer on a surface thereof and a grating in the waveguide. The grating has a period such as to deflect light passing along the waveguide out of the optical device. The angle at which the light is emitted from the waveguide can be varied by varying the index of refraction of the material of the waveguide under the grating. This can be achieved by applying a voltage across the waveguide.

Abstract: A flash-type analog-to-digital converter (ADC) uses only 2.sup.n-m comparators coupled to the analog input line to generate a n-bit digital output signal. Each pair of these actual comparators are coupled, in parallel, to 2.sup.m pseudocomparators which provide values representing comparisons of the input signal value to respective reference values between the reference values used by the actual comparators. The output signals of each pair of actual comparators are combined in respectively different proportions at each of the pseudocomparators. In this manner, the output signals of the actual comparators are averaged to produce the interstitial comparison values. In one embodiment of the invention, the ADC is implemented in BiCMOS technology with a bipolar differential input stage and a CMOS latching comparator. Signals are distributed from the actual comparators to the pseudocomparators via a pair of resistive ladder networks.

Abstract: A low breakdown voltage device for protecting an integrated circuit from transient energy is disclosed. This device provides an SCR having a reduced "snap-back" trigger voltage compatible with submicron integrated circuit fabrication processes. A low breakdown voltage SCR protection circuit is also disclosed.

Abstract: A management tool is disclosed which aids the user in controlling the flow of data from one database table to another in computer memory, particularly when both the potential amount of data and the number of programmed functions which can be performed upon or be controlled by the data are large.

Abstract: There is disclosed an ADC including a comparator which sets, bit-by-bit, a successive approximation binary register. Feedback means for auto-biasing, auto-calibration, and offset compensation within the ADC are provided. The ADC sets itself to a high degree of accuracy automatically by reference to a master voltage reference. A number of identical ADCs are connected in parallel to provide an increased sampling rate. The ADC architecture compensates for component tolerance differences, for common mode noise, and for secondary parasitic effects. The ADC operates with high resolution at high speed (e.g., 10 bits at 50 MHz), and can be implemented in MOS technology with good circuit yield and is compatible with ASICs.

Abstract: There is disclosed an ADC including a comparator which sets, bit-by-bit, a successive approximation binary register. Feedback means for auto-biasing, auto calibration, and offset compensation within the ADC are provided. The ADC sets itself to a high degree of accuracy automatically by reference to a master voltage reference. A number of identical ADCs are connected in parallel to provide an increased sampling rate. The ADC architecture compensates for component tolerance differences, for common mode noise, and for secondary parasitic effects. The ADC operates with high resolution at high speed (e.g., 10 bits at 50 MHz), and can be implemented in MOS technology with good integrated circuit chip yield and is compatible with new ASICs.

Abstract: A spatio-temporally oriented coring method and apparatus for reducing noise in a sequence of images is disclosed. The method comprises the steps of decomposing each image into low-pass and a prefiltered sub-images, decomposing each prefiltered sub-image into a plurality of component patterns which are oriented in space, time or a combination of space and time, filtering each oriented component pattern to form a plurality of filtered patterns and reconstructing the image from the filtered patterns and the low-pass sub-image. Apparatus for reducing the noise in a sequence of images comprises means for decomposing each image into low-pass and prefiltered sub-images, means for decomposing each prefiltered sub-image into a plurality of component patterns which are oriented in space, time or a combination of space and time, means for filtering each component pattern to form a plurality of filtered patterns, and means for reconstructing the image from the filtered patterns and the low-pass sub-image.

Abstract: The invention is a method for determining the motion of an image sensor through a scene directly from brightness derivatives of an image pair. A global image sensor motion constraint is combined with the local brightness constancy constraint to relate local surface models with the global image sensor motion model and local brightness derivatives. In an iterative process, the local surface models are refined using the image sensor motion as a constraint, and then the image sensor motion model is refined using the local surface models as constraints. The analysis is performed at multiple resolutions to enhance the speed of the process.

Abstract: A computer analysis tool enables an operator to analyze and visualize more effectively data objects having a large number of individual physical attributes. In the tool, one or more visual attribute icons are generated on the screen of a display monitor. Each of the visual attribute icons displays values of a sub-set of the total physical attributes of the data objects residing in computer memory in terms of different graphic characteristics. In addition, a physical attribute icon is generated for each of the data objects and may be selectively displayed on the screen of the monitor. Each physical attribute icon identifies all of the physical attributes of its data object available in computer memory. The operator selects from the physical attribute icons, typically with the aid of an input device such as a mouse, the sub-sets of physical attributes to be displayed in the visual attribute icons.

Abstract: A routing process for a single-instruction-multiple-data (SIMD) multi-level hierarchical network of nodes, which are arranged in clusters and interconnected by dual, unidirectional channels, are used to send data packets including routing address information during a succession of routing cycles from transmitting ones to receiving ones of a large number of parallel processors (e.g., 4096 processors arranged in a hierarchy of 8 cabinets, each of which contains a cluster of 8 circuit boards, with each circuit board containing a cluster of 64 processors). Each of the nodes includes a storage buffer having a capacity equal to a given number which is one more than the total number of channels terminating at that node. This routing process guarantees prevention of deadlock between levels and buffer overflow, and offers high-speed, low-cost interprocessor communication for SIMD computers.

Abstract: A novel ceramic green tape composition useful in the manufacture of silver conductor based, low temperature, co-fired multilayer circuit boards comprises from about 8-35% by weight of a calcium-zinc-aluminum-borosilicate devitrifying glass; from about 10-35% by weight of a low alkali borosilicate glass; from about 10-35% by weight of a lead-zinc-aluminosilicate glass; from about 10-35% by weight of a ceramic filler; up to 0.5% by weight of a coloring agent and from about 20-45% by weight of an organic binder. The co-fired multilayer circuit boards made from these green tape compositions have excellent mechanical and electrical properties and have thermal expansion characteristics matching that of silicon.The devitrifying glass comprises from about 10-30% by weight of zinc oxide; from about 10-20% by weight of calcium oxide; up to about 15% by weight of boron oxide; from about 15-20% by weight of aluminum oxide and about 25-55% by weight of silicon oxide.

Abstract: By processing the highest-resolution graphical data (e.g., image data) pertaining to relevant-objects defined by the graphical data into abstracted multiple-attribute information that is stored in a group of nodes of the lowest level of a hierarchy of data arrays (e.g., the leaf nodes of a complete data tree file), the present invention processes the data of each of these hierarchy of data arrays backward toward a single node of the highest level of the hierarchy of data arrays (e.g., the root node of a complete data tree file), to derive an attribute vector of all the abstracted multiple-attribute information at this single node. The derived attribute vector is then used to guide a search down the hierarchy of data arrays from the single node of its highest level toward at least a selected one of the group of nodes of its lowest level (which, by way of example, may correspond to the location of a likely relevant object).

Abstract: An acoustic transducer which can be made small in size, i.e., in width, length and thickness, so as to fit into a credit card size package. The transducer comprises a flat frame having an opening therethrough. A pair of diaphragms of a piezoelectric plastic material extend across the opening in the frame along opposite sides of the frame. The diaphragms are stretched in at least one direction and are bonded to the frame under tension in the direction of the stretch. The diaphragms are bonded together at a position within the opening in the frame. The diaphragms are coated in both surfaces with conductive metal films. The inner metal films on the diaphragms which are opposed to each other are electrically connected together and the outer metal films are electrically connected together.

Abstract: An X-Y addressable imager utilizes a gate connection of a source-follower-connected MOSFET to isolate inherent capacitance of each horizontal signal line of the imager from a vertical signal line that couples the MOSFETs to a common output circuit, including a load resistor for the source followers. In one embodiment the horizontal signal lines are assigned to different groups, and each group is coupled through a different one of plural vertical signal lines to the common output circuit. At least one multiplexer couples one vertical signal line at a time to the common output circuit. Also shown is imager array scanning logic for effecting variable integration of array pixels.

Abstract: The effective light incident upon pixels of an X-Y addressable imager is controlled by electrically controlling the effective photonic charging time of each pixel in each frame time of operation. The horizontal signal lines of the imager are assigned to different groups, and each group is coupled through a different one of plural vertical signal lines to a common output circuit. A multiplexer couples one vertical signal line at a time to the common output circuit. Imager array scanning logic is provided for recurrently selecting pixels of two of the horizontal signal lines at a time, but connecting only one of them to its vertical signal line at that time, for effecting variable integration by array pixels.

Abstract: A semiconductor light emitter comprising a substrate of a semiconductor material having a pair of opposed surfaces and a body of semiconductor material on one of the surfaces. The body includes a pair of clad layers of opposite conductivity types having an intermediate quantum well region therebetween. The clad layers are of a semiconductor material which forms a heterojunction with the material of the quantum well region. The clad layers and the quantum well region form a waveguide which extends along the body. A plurality of gain sections are formed in the body spaced along and optically coupled by the waveguide. Each of the gain sections is adapted to generate light therein when a voltage is placed thereacross. One of the gain section has gratings at each end thereof which are adapted to reflect light back into the one gain section and thereby create a beam of light.

Abstract: A novel devitrifying glass comprising, in weight percent, from 5-15% of zinc oxide, from 10-18% of magnesium oxide; from 15-20% of calcium oxide; from 6-14% of barium oxide; from 15-20% of aluminum oxide and from 30-40% of silicon dioxide. The glasses are thermally matched to alumina substrates. The glasses form overglaze thick film inks when admixed with an organic vehicle that are useful as protective coatings for alumina substrates and multilayer printed circuits.

Abstract: A drive circuit for a liquid crystal display converts a display information signal to an n bit gray scale code to control the brightness at a prescribed pixel. A counter receives the m most significant bits of the n bit gray scale code and a latch receives the n-m least significant bits of the n bit gray scale code. The counter is decremented by clock pulses occurring at predetermined intervals and a set of 2.sup.n-m sub-interval timing signals are generated in response to each clock pulse. A transfer gate is enabled by an interval initiating pulse to permit charging of the pixel. One of the sub-interval timing signals is selected in response to the n-m least significant bits of the n bit gray scale code stored in the latch. The transfer gate is disabled by the sub-interval timing signal immediately succeeding the decrementing of the counter to its zero state.