Abstract: A level shifter circuit has a pair of voltage buses, first and second p-channel MOS transistors and third and fourth n-channel MOS transistors. Each transistor has a gate to control conduction. The first and third transistors are connected in series between the voltage buses and the second and fourth transistors are connected in series between the voltage buses. A node between the first and second transistors is connected to the gates of the second and fourth transistors. An input signal having one of first and second levels is applied to the gate of the first transistor while the inverse of the input signal is applied to the gate of the second transistor. One voltage bus is connected through one of the second and fourth transistors in response to the first level input signal. The other voltage bus is connected the other of the second and fourth transistors in response to the second level input signal.

Abstract: A process is disclosed for forming bipolar transistors in a BiCMOS process which is fully compatible with the CMOS process used to form other devices in the same integrated circuit. The process produces bipolar transistor sizes which are compatible with the minimum size features and design rules of the CMOS process. A CVD silicon oxide layer to be used to form spacers is deposited on the top of emitter and gate electrodes covered with a first oxide layer.

Abstract: Low-expansion devitrifying glass compositions exhibiting a negative-slope temperature coefficient of expansion over a temperature range from about 125.degree. C. to about 500.degree. C. are useful for the fabrication of thick film copper via-fill inks for multilayer printed-circuit boards.

Abstract: A Liquid Crystal Display device has first and second transparent substrates with a liquid crystal material sealed therebetween; a centrally disposed optically active display region having a matrix of pixels and a first and second scanner, and a transparent common electrode formed on the inner surface of the first and second transparent substrates, respectively; and a power supply and data signal distribution region surrounding at least a portion of the optically active display region and near the first and second scanners. The power supply and data signal distribution region comprises (a) a groove, and (b) a plurality of parallel conductors, formed on the inner surface of the second and first transparent substrates, respectively, which conductors include a height extending into the groove to reduce each conductor's resistance.

Abstract: A device for protecting an integrated circuit from transient energy is disclosed. This device provides an SCR having a reduced "snap-back" trigger voltage.

Abstract: An iterative process, implemented by a feedback loop, responds to all the image data in the respective analysis regions of three consecutive frames of a motion picture, to provide, after a plurality of cycles of operation thereof, an accurate estimation of the motion of either one or both of two differently moving patterns defined by the image data of these respective analysis regions. The analysis region of each frame is preferably large, and may occupy the entire frame area of a frame. The type of differently moving patterns include (1) separation by a motion bounty, (2) overlapping transparent surface in motion, (3) "picket fence" motion (4) masking of a small and/or low-contrast pattern by a dominant pattern, and (5) two-component aperture effects. Also, the operation of this iterative process inherently accurately estimates the motion of image data defining a single moving pattern.

Abstract: A liquid crystal device (LCD) display includes a grid of conductive row select lines and column data lines which are used in conjunction with thin-film transistors (TFT's) to address pixel electrodes in the display. The LCD display includes two shift registers for receiving and propagating the select signals for the row select lines, each shift register has a plurality of shift register stages, one connected to each row select line. A plurality of combiner circuits are provided, one for each stage of each of the shift registers. Each combiner circuit is configured to provide an electrical conduction path for the select signal between successive stages in each of the shift registers. When a fault is detected in a stage of one of the shift registers, the combiner circuit coupled to the output of the defective stage reconfigured to route the select signal from the corresponding stage of the other shift register to the next stage of the one shift register.

Abstract: A time series of successive relatively high-resolution frames of image data, any frame of which may or may not include a graphical representation of one or more predetermined specific members (e.g., particular known persons) of a given generic class (e.g. human beings), is examined in order to recognize the identity of a specific member if that member's image is included in the time series. The frames of image data may be examined in real time at various resolutions, starting with a relatively low resolution, to detect whether some earlier-occurring frame includes any of a group of image features possessed by an image of a member of the given class.

Abstract: A liquid level and composition sensor includes a first interdigitated capacitor mounted substantially vertically in a tank, and a second interdigitated capacitor mounted substantially horizontally in and near the bottom of the tank. An electronic processor is responsive to the value of capacitance of the first capacitor for producing a first voltage signal proportional to the level of the liquid in the tank and is responsive to the value of capacitance of the second capacitor for producing a second voltage signal having a voltage level corresponding to the composition or dielectric constant of the liquid. The processor also multiplies the first and second voltage signals together to produce a liquid level voltage output signal having a constant slope for voltage amplitude versus liquid level, regardless of the composition of the liquid in the tank.

Abstract: The optoelectronic interconnection of the present invention provides a means for interconnecting a plurality of integrated circuits and each having at least one termination. The termination includes a transmitting section and a receiving section. Each transmitting section includes means for converting an output electrical signal from the integrated circuit to an optical signal in the form of a beam and an output grating for emitting the optical beam from the integrated circuit. Each receiving section includes an input grating for receiving an input optical signal in the form of a beam, means for amplifying the optical signal and a photodetector for converting the optical signal to an electrical signal which is fed to the circuit. The integrated circuits may be mounted adjacent each other with the output signals being emitting from the integrated circuits in the same direction.

Abstract: A protection device for an integrated circuit includes short and longer channel length structures, each of which provides a parasitic bipolar transistor, connected between a terminal of the integrated circuit and a source of reference voltage. The short channel length structure has a breakdown voltage greater than the supply voltage for the integrated circuit, and less than the insulator damage threshold of the integrated circuit. The conduction through the short channel length structure after initiation of a transient phenomena causes the longer channel length structure to conduct before the transient exceeds the breakdown voltage of the integrated circuit and the short channel length structure. The longer channel length structure operatges in the "snap-back" conduction mode when the current density exceeds a critical value to conduct away the transient energy.

Abstract: A redundancy circuit that substitutes a redundant circuit element for a corresponding defective circuit element includes a severable fuse link and a redundancy control circuit with an input connected to the severable fuse link and first and second outputs. When the fuse link is intact, the first output of the redundancy control circuit is in a first state and the second output is in a second state. When the fuse link is severed, a momentary signal on power up places the first output in the second state and the second output in the first state. The first output is coupled to the one circuit element and the second output is coupled to the corresponding redundant circuit element. If the one circuit element is defective, it is disabled by severing the fuse link.

Abstract: In the manufacture of printed circuit boards, a first photoresist post is patterned on the substrate where via holes are to be made. A dielectric layer is put down, a second photoresist layer patterned so as to have openings over and in alignment with the photoresist posts, and the dielectric removed from the via holes. Barrier layers to reduce interaction between layers of copper, dielectric and photoresist during filling of the via holes with a conductor via fill ink are also described.

Abstract: An optical amplifier comprising a substrate of a semiconductor material having a pair of opposed surfaces and a body of semiconductor material on one of the surfaces. The body includes a pair of clad layers of opposite conductivity types having an intermediate quantum wall region therebetween. The clad layers are of a semiconductor material which form a heterojunction with the material of the quantum well region. The clad layers and quantum well region forms a waveguide which extends along the body. A gain section is in the body along the waveguide. The gain section includes a capping layer over the outermost clad layer, a contact on the capping layer and a contact on the other surface of the substrate to allow a voltage to be applied across the gain section. The gain section is adapted to generate light in the active region when a voltage is applied thereacross. A light input section having a grating extending across the body is at one end of the gain section.

Abstract: A frequency divider receives a first frequency signal and at least one clock signal of a sub-multiple of the first frequency. The first frequency signal charges a storage terminal once each first frequency cycle and the sub-multiple frequency signal discharges the storage temrinal once each sub-multiple frequency cycle. The discharged storage terminal sets the frequency divider output which is reset by the first frequency signal when the storage terminal is discharged. The sub-multiple frequency clock signal is employed to control the storage terminal instead of a feedback path from the output to increase the operating frequency of the divider.

Abstract: A protection structure comprises a semiconductor substrate of a first conductivity type with a region of second conductivity type in the substrate at the surface thereof. A region of second conductivity type has disposed therein first and second regions of the second conductivity type, a third region of the first conductivity type adjacent the surface of the substrate, and a fourth region of the second conductivity type adjacent the substrate surface adjacent the third region. A shallow field region extends a distance into the region of second conductivity type between the first and second regions. A first electrical contact overlies the surface of the first region and a second electrical contact overlies the third and fourth regions.

Abstract: The present invention relates to an optoelectronic integrated circuit having a substantially planar surface and which includes at least one laser diode and at least one field effect transistor. The integrated circuit comprises a substrate of semi-insulating GaAs having on a surface thereof in succession a first clad layer, a first confinement layer, a quantum well active layer, a second confinement layer, a second clad layer and an FET active layer. The FET active layer is of a material having good field effect transistor characteristics, such as N type GaAs or N type A1GaAs over a layer of undoped GaAs. The quantum well active layer is formed of alternating layers of undoped GaAs and a material which is capable of generating light of a wavelength longer than can be absorbed by the FET active layer, such as undoped InGaAs. The laser diode includes spaced contact regions of opposite conductivity type extending through the layers to the quantum well active layer.

Abstract: A circuit that compensates for threshold voltage variations in a large array of deposited thin film MOS transistors includes a threshold voltage compensation transistor for a subset of the deposited analog thin film transistors having a prescribed source to gate threshold voltage. The source electrode of the threshold voltage compensation transistor receives a voltage corresponding to the maximum threshold voltage in the large array. The gate and drain electrodes of the threshold voltage compensation transistor are connected together and to one terminal of a capacitor. The other terminal of the capacitor is connected to a second voltage and the capacitor is momentarily discharged to set the threshold voltage compensation transistor gate and drain electrodes to the second voltage. The gate and drain electrodes of the threshold voltage compensation transistor are connected to the gate electrodes of the subset of analog thin film transistors.

Abstract: A CMOS device is provided with a field shield region below one of the P and N channel MOS transistors, whereby the field shield region is formed to have the opposite conductivity of both the one MOS transistor it underlies, and of the substrate, thereby permitting the field shield region to be biased to a potential for turning off any anomalous back channel leakage current in the one MOS transistor, and also permitting the substrate to be biased to an opposite polarity for turning off such leakage current in the other MOS transistor.

Abstract: A diode laser array comprises a substrate of a semiconductor material having first and second opposed surfaces. On the first surface is a plurality of spaced gain sections and a separate distributed Bragg reflector passive waveguide at each end of each gain section and optically connecting the gain sections. Each gain section includes a cavity therein wherein charge carriers are generated and recombine to generate light which is confined in the cavity. Also, the cavity, which is preferably a quantum well cavity, provides both a high differential gain and potentially large depth of loss modulation. Each waveguide has a wavelength which is preferably formed by an extension of the cavity of the gain sections and a grating. The grating has a period which provides a selective feedback of light into the gain sections to supporting lasing, which allows some of the light to be emitted from the waveguide normal to the surface of the substrate and which allows optical coupling of the gain sections.