Abstract: The present disclosure relates to a method for electronic design verification. Embodiments may include receiving, using at least one processor, an electronic design and performing formal verification upon at least a portion of the electronic design. Embodiments may further include identifying one or more violations associated with the formal verification and ranking the one or more violations, based upon, at least in part, one or more user-selectable variables. Embodiments may also include displaying, at a graphical user interface, the one or more violations in a ranked order.

Abstract: Disclosed is an improved approach to implement training for memory technologies, where a data valid window is re-determined using boundary information for a new data valid window. The information obtained for the new location of the first edge is used to minimize the computational resources required to identify the location of the second edge. This greatly improves the efficiency of the process to perform the re-training.

Abstract: The present disclosure relates to an apparatus and method for correcting a duty cycle of at least one signal. The apparatus may comprise at least one set of inverters configured to receive the at least one signal and correct the duty cycle of the at least one signal at a correction location of a plurality of correction locations based upon, at least in part, a transmission rate mode of a plurality of transmission rate modes.

Abstract: The present disclosure relates to a method for electronic design verification. Embodiments may include receiving, using at least one processor, an electronic design and automatically identifying one or more code coverage points from a netlist of an original model associated with the electronic design. Embodiments may include receiving a property and one or more elements, each of the one or more elements corresponding to one of the one or more code coverage points. Embodiments may further include performing model checking based upon, at least in part, the property and the one or more elements. Embodiments may also include verifying the property and generating an unsatisfiability core based upon, at least in part, the one or more elements.

Abstract: Embodiments relate to systems, methods, and computer-readable media to enable design and creation of receiver circuitry. One embodiment is a receiver apparatus comprising a plurality of receiver arrangements, each receiver arrangement having a sampling circuit and a multi-stage differential amplifier connected to the sampling circuit. Each receiver arrangement is configurable via switches between an amplifying mode and an autozero mode. Control circuitry may select output data from receiver arrangements that are not in autozero mode using multiplexer circuitry. In various embodiments, settings for individual receiver arrangements may be set based on decision feedback equalization (DFE).

Abstract: A method for identifying a potential cause of a failure in simulation runs on a design under test (DUT) using machine learning is disclosed.

Abstract: A method for functional safety verification for use in a verification of a design under test (DUT), includes obtaining a set of verification tests previously executed on the DUT and related execution data; injecting a fault into each of the tests of the set of verification tests; analyzing a hierarchy tree representation of the DUT from top down to identify clusters of faults under child nodes of the hierarchy tree; and for each of the clusters of faults, based on the execution data, performing test ordering of tests from the set of verification tests according to likelihood of classifying the faults under the child node in which that cluster is located.

Abstract: The present disclosure relates to a method for electronic circuit design. Embodiments may include receiving, using a processor, an electronic circuit design and identifying at least one combinational loop associated with the electronic circuit design. Embodiments may also include extracting, for each component of the loop, a set of logic conditions and modeling the at least one combinational loop. Embodiments may further include providing a graphical user interface configured to display one or more constraint candidates and determining whether or not a conflict exists between constraint candidates. Embodiments may also include ranking the constraint candidates, based upon, at least in part, a number of loops disabled and one or more disabled loop characteristics.

Abstract: An exemplary emulation computer may allocate a portion of its emulation memory for capturing probe data during a runtime of emulating a device under test (DUT). The emulation computer may instantiate a plurality of streaming probes from dynamic netlists provided by a user. The streaming probes may capture non-transitory internal signals within the DUT and transmit the captured non-transitory internal signals to the allocated portion of the emulation memory, which in turn may store the received signals as waveform data records. During the runtime of emulating the DUT, the emulation computer may receive an upload request for the waveform data records from a workstation computer. In response to the request, the emulation computer may transmit the waveform data records to the workstation computer. The emulation computer does not have to pause or stop the runtime of emulating the DUT while transmitting the data records to the workstation computer.

Abstract: Disclosed herein is an apparatus and method for emulating hardware. The apparatus includes a data array configured to store input data for an emulation cycle and a carry chain coupled to the data array receives one or more inputs from the data array. The carry chain is configured to generate output data in response to performing an arithmetic operation by a set of configurable logic gates using the one or more inputs in a pre-determined number of clock cycles. One or more processors are coupled to the carry chain and the data array, and are configured to emulate a logic gate function using at least the input data from the data array or the output data from the carry chain.

Abstract: The present disclosure relates to a computer-implemented method for analyzing one or more hyper-parameters for a multi-layer computational structure. The method may include accessing, using at least one processor, input data for recognition. The input data may include at least one of an image, a pattern, a speech input, a natural language input, a video input, and a complex data set. The method may further include processing the input data using one or more layers of the multi-layer computational structure and performing matrix factorization of the one or more layers. The method may also include analyzing one or more hyper-parameters for the one or more layers based upon, at least in part, the matrix factorization of the one or more layers.

Abstract: The present disclosure relates to an apparatus including level shifter circuitry configured to convert a voltage between one or more multi-voltage domains. The apparatus may include an integrated circuit having a cross-coupled latch including a first weak transistor cross-coupled with a second weak transistor. The integrated circuit may further include a first strong transistor in parallel with the first weak transistor and a second strong transistor in parallel with the second weak transistor. The integrated circuit may further include an inverter configured to toggle at least one of the first weak transistor and the second weak transistor.

Abstract: An emulation system comprises an outband traffic generating device comprising at least one field programmable gate array coupled to a host system. The outband traffic generating device is configured to transfer one or more bits via an outband channel to a register of an inband traffic generating device. The inband traffic generating device comprises at least one field programmable gate array coupled to a target system. The inband traffic generating device is configured to transfer the one or more bits via an inband channel to the outband traffic generating device.

Abstract: Embodiments include herein are directed towards a method for generating an input/output model from a SPICE (Simulation Program with Integrated Circuit Emphasis) netlist. Embodiments may include receiving, using a processor, a SPICE netlist associated with an electronic design and selecting at least a portion of the SPICE netlist for analysis. Embodiments may further include reading the selected portion of the SPICE netlist and rendering a schematic symbol corresponding to the selected portion of the netlist. Embodiments may also include performing one or more operations associated with the schematic symbol and translating the one or more operations into simulation commands.

Abstract: A method for automated selection of a subset of a plurality of validation tests for testing a device under test (DUT), may include obtaining the plurality of validation tests; using a processor, obtaining from a user, via an input device, one or a plurality of conditions relating to one or a plurality of execution parameters; and using a processor, analyzing each of the validation tests to identify a subset of the validation tests that includes verification tests conforming to said one or a plurality of conditions.

Abstract: Disclosed herein are embodiments of systems, methods, and products for dynamically determining and rendering a target resistance of a partially routed net between two circuit devices in an integrated circuit (IC) design and automatically resizing a wire segment being edited in real time based on the target resistance such that the fully routed net satisfies the maximum resistance constraint. Therefore, the embodiments disclosed herein simplify the circuit designer's job and improves design productivity. Unlike conventional systems, an EDA tool disclosed herein does not have to route the full net between two circuit devices to run design rule checking (DRC). Thus, the EDA tool does not require multiple iterations of fully routing a net and checking for DRC violations such that the maximum resistance constraint is not violated.

Abstract: Described herein is an improved approach to implement routing for electrical designs. A structural routing solution is provided, where a routing system is implemented to generate a complete routing tree. A user interface is provided that captures users' design intent about topology of an electrical design, and the routing system adheres to that user's design intent about the topology throughout a layout process for the electrical design.

Abstract: The present disclosure relates to a method for formal verification of an electronic design. Embodiments may include receiving, using a processor, an electronic design having a plurality of clock configurations associated therewith and identifying a target clock configuration associated with the electronic design. Embodiments may also include receiving a range of clock factor values from a user, wherein each clock factor value corresponds to a frequency of the target clock configuration. Embodiments may further include selecting, via a formal engine, at least one clock factor value from the range and selecting, via the formal engine, at least one clock phase associated with the target clock configuration. Embodiments may also include performing formal verification of the electronic design, based upon, at least in part, the at least one clock factor value or the at least one clock phase.

Abstract: Disclosed is an approach to implement snapping techniques that aid the interactive, assisted, or automatic placement of layout instances or groups of layout instances for generating a legal placement layout while reducing or entirely eliminating any subsequent or separate performance of design rule checking with respect to the relevant design rules, constraints, or requirements governing the legality of the instances or groups of instances placed in the placement layout.

Abstract: The present disclosure relates to a computer-implemented method for visualizing one or more IP-XACT component data routes is provided. The method may include receiving, using at least one processor, an IP-XACT description of one or design elements including at least one target ingress interface, and at least one of an initiator egress interface, a memory map and an address space. The method may further include analyzing, using the at least one processor, the IP-XACT description of the one or design elements and displaying a graphical user interface, based upon, at least in part, the IP-XACT description of one or design elements, wherein the graphical user interface is configured to display the at least one target ingress interface, and any number of the initiator egress interface, the memory map and the address space.