Abstract: An improved approach is provided to implement performance checking. A check is performed as to whether two designs are equivalent without needing to analyze their outputs on a cycle-by-cycle basis, where the two designs are checked to see if they are equivalent on the transaction-level. Thereafter, the outputs for the transactions are analyzed relative to delay time periods, which allows verification and identification of possible performance issues and differences between the two designs.

Abstract: A system and method are provided for establishing an automated debugging environment in an Electronic Design Automation (EDA) work flow. A user interface is provided for interfacing with a user by displaying a list of debuggable parameters, accepting a selection thereof from a user, and automatically locating both the callback function which sets the selected parameter, and the source code file which contains the callback function. Additionally, it is determined whether the callback function sets solely the selected parameter, or several different parameters, and an automatic breakpoint is set accordingly to break only responsive to the selected parameter. On execution of the modified callback function, execution will be arrested by the automatically-set intelligent breakpoint and a debugging user interface will be generated and provided to the user with a display of the relevant source code, callback function, parameter names and values, system state, and the like.

Abstract: A method is provided to narrow down the exponent range throughout most part of the division and square root calculations, to make both software assistance and precision extension unnecessary. The method adjusts the exponent at the end of the calculation to reach IEEE-754 results.

Abstract: Disclosed are methods, systems, and articles of manufacture for implementing electronic circuit designs with electro-migration awareness. Some embodiments perform schematic level simulation(s) to determine electrical characteristics, identifies physical parasitics of a layout component, determines the electrical or physical characteristics associated to electro-migration analysis on the component, and determines whether the component meets EM related constraint(s) while implementing the physical design of the electronic circuit in some embodiments. Some embodiments further determine adjustment(s) to the component or related data where the EM related constraints are not met and/or and present the adjustment(s) in the form of hints. Various data and information, such as currents in various forms or voltages, are passed between various schematic level tools and physical level tools.

Abstract: A method and system are provided for utilizing inter-application image overlays or virtual transparent overlays (VTOs) to communicate information between users and tools along the EDA tool chain in an EDA design flow. VTOs remain divorced from an underlying design file and are able to be manipulated by a plurality of different users in a plurality of different EDA applications or tools, all meant to operate in different stages of the design flow and perform different functions along the design path towards actual physical circuit realization and fabrication.

Abstract: A system and method are provided for selective application and expeditious reconciliation of constraints within a hierarchy of circuit design constraints. A semi-transparent constraint editor user interface is provided in contextual registration near detected violations during editing interactions with a circuit design. The constraint editor provides a simplified representation of a lookup order of a hierarchy of constraints applicable to an object related to the detected violation. The user is then able to easily modify constrained values within the lookup order, modify the lookup order, or modify the editing interaction to reconcile the violation expeditiously all while maintaining context within the circuit design.

Abstract: Disclosed is a method and system for translating parameterized cells (pcells) that are created using different programming languages. The pcell source code created in a first programming language undergoes a translation process to translate that source code to a second programming language. A validation process is also provided to ensure the correctness of the translations.

Abstract: The present patent document relates to a method and apparatus for modeling a flip-flop of a user's circuit design when that circuit design is mapped in a hardware functional verification system including a plurality of interconnected emulation chips, or in a single emulation chip. The flip flop can be modeled in the emulation chip as two stages using only a single instruction, and may be configured by programming a register set. A data block, enable block, and LUT block are provided to model the flip flop, and may operate in one of several modes, including combined and uncombined modes. The data block includes a data array to store and provide previous data inputs and previous states of the modeled flip flop. The disclosed embodiments allow a more efficient use of LUTs for modeling flip flops, including options for resets and global enables, operating in several modes.

Abstract: A method and system of providing additional lookup tables in an emulation processor cluster of an emulation chip of a hardware functional verification system is provided. An indirection table may be used within the processor cluster to provide the commonly-used function tables for the lookup tables (LUTs). The indirection table may be indexed according to a smaller portion of the standard LUT function table provided by an instruction than otherwise needed. The unused function table bits in the instruction may then be used for other purposes, including providing functionality to one or more extra LUTs of the processor cluster, whose function tables may be provided from another indirection table provided for that purpose. Additional processing capacity may thereby be provided for the cluster with a small amount of additional overhead within the emulation chip, while still providing the full range of function tables of the LUTs.

Abstract: An apparatus and method is described for low skew phase generation for multiplexing signals using limited global low skew lines on a multiple FPGA system. The apparatus includes a reference clock programmed to generate a clock signal and programmable logic devices. The programmable logic devices include I/O terminals, combinational logic coupled to the I/O terminals, programmable logic coupled to the combinational logic, a phase generator programmed to receive the clock signal from the reference clock and to generate a phase clock based on the clock signal and a plurality of phase enable signals based on the phase clock, low skew lines to distribute the phase enables with minimal skew caused by routing delays, and flip-flops programmed to have a clock input driven by the phase clock, a data input coupled to ground, and a data output coupled to the combinational logic.

Abstract: A method and system of dynamically selecting a memory read port are provided. In one form a method may comprises, in part, processing instructions in the emulation processors of a hardware functional verification system, storing output bits generated by the LUT in a plurality of storage elements, selecting between a plurality of previously-stored LUT output bits and the output port of the data memory, selecting one of the plurality of output bits stored in the storage elements, and sending the current data bit provided at the output port of the data memory to a selection circuit when previously-stored LUT output bits are provided. The disclosed systems and methods provide the ability all inputs to a LUT, even while a memory read port is occupied performing other operations during that emulation step, for example sending a value stored in the memory to another emulation processor using the selection circuit.

Abstract: The present invention provides a method for compensating infidelities of a process that transfers a pattern to a layer of an integrated circuit, by minimizing, with respect to a photomask pattern, a cost function that quantifies the deviation between designed and simulated values of circuit parameters of the pattern formed on a semiconductor wafer.

Abstract: A sink circuit for protecting connectivity of a digital multimedia interface, the sink circuit is connected in a sink multimedia device. The sink circuit comprises a sink port configured to provide a connection to a source multimedia device; a termination coupled to the sink port; and a protection component coupled in series between the termination and a power source of the sink multimedia device, the protection component blocks any direct current path through the sink port when the sink multimedia device is off and the power source of the source multimedia device is on.

Abstract: Various processes or modules described herein enable the schematic design tools to obtain physical data of a physical design and to perform one or more simulations in the schematic domain with such physical data such that the schematic design tools are made electrically aware of the physical data. Various types of data in the physical domain may be transferred to the schematic domain for the performance of one or more schematic simulations with the transferred data. The schematic designs are thus made electrically aware of such data from the physical domain and may incorporate any layout induced effects early in the schematic design stage or even at the time a schematic instance of a physical module is to be created in the schematic domain.

Abstract: A time to digital converter with a successive approximation architecture (300) and a method thereof is provided. The time to digital converter (300) includes successive approximation analog to digital converter circuitry (310) configured for converting the differential voltage established in the digital to analog converter (305) of the successive approximation analog to digital converter circuitry (310) to a digital representation thereof, where the differential voltage corresponds to a measured time period representing a time difference between receipt of leading edges of two signals. Time to digital converter (300) may incorporate a current switching unit (340?) having a plurality of current switching circuits (303a-303n, 304a-304n) arranged in parallel to increase the precision of digital time output of time to digital converter (300). The plurality of current switching circuits (303a-303n, 304a-304n) can be selectively enabled to alter the sensitivity of the time to digital converter (300).

Abstract: Disclosed are methods, systems, and articles of manufactures for implementing correct-by-construction physical designs with multiple-patterning-awareness by identifying a first set of grids for a layer based at least in part upon characteristics of other layer(s), identifying a set of tracks for the layer to implement the physical design for the layer, and implementing a shape in the physical design by at least terminating an end of the shape at a grid of the identified first set of grids. The end of the shape may be extended or contracted from its as-design location to the grid. The physical design thus implemented is correct-by-construction and is free of violations of one or more directional design rules.

Abstract: Various embodiments automatically back annotate an electronic design representation by inserting complex model instances in the representation and interconnecting the model instances with one or more interconnect models. Identifications of ports in a first representation may be associated or updated with identifications of corresponding ports in a second representation. Annotating the first representation may also include associating or stitching parasitic information from the second representation with or in the first representation. A model is used to represent a vectored net by splitting a vectored net with a vectored net identification into multiple scalared net segments each having its own scalared net identification. Some aspects automatically generate a display for visualizing results of annotating an electronic design with complex models. Some of these aspects may further include parasitic information and analysis results in the display.

Abstract: Various embodiments implement additional connectivity for electronic designs by identifying one or more regions for a route in normal connectivity of an electronic design, identifying a plurality of seeding segments from the route based at least in part upon the one or more regions, identifying a plurality of additional nodes in the plurality of seeding segments, and generating one or more additional routes connecting the plurality of additional nodes in the plurality of seeding segments. The one or more additional routes are generated without disturbing the normal connectivity including a plurality of Steiner points and the route. Additional nodes differ from Steiner points and are used to implement additional routes that belong to a different route type.

Abstract: Disclosed are techniques to analyze multi-fabric designs. These techniques generate a cross-fabric analysis model by at least identifying first design data in a first design fabric of a multi-fabric electronic design using a first session of a first electronic design automation (EDA) tool, update the cross-fabric simulation model by at least identifying second design data in a second design fabric using a second session of a second EDA tool, and determine analysis results for the multi-fabric electronic design using at least the cross-fabric simulation model. Analysis results may be determined using parasitic, electrical, or performance information.

Abstract: In one embodiment of the invention, a method of physical clock topology planning for designing integrated circuits is disclosed. The method includes reading an initial placed netlist of an integrated circuit design and a floorplan of the integrated circuit design, analyzing the integrated circuit design to determine potential enable signals to gate clock signals that clock the plurality of flip flops to reduce power consumption; simultaneously optimizing and placing the clock enable logic gates to gate clock signals to the plurality of flip flops; and minimizing timing variation of the clock signals to the plurality of flip flops.