Abstract: A home multimedia network comprises a plurality of source nodes, wherein each of the source nodes includes an apparatus for concurrently transmitting and receiving high-speed data services; a plurality of sink nodes, wherein each of the sink nodes includes the apparatus for concurrently transmitting and receiving high-speed data services; a switch for connecting a first group of the plurality of source nodes located at one room to one or more sink nodes located at a different room than the first group of source nodes, the first group of source nodes and the one or more sink nodes are connected to the switch through a twisted-pair cable, the high-speed data services are concurrently transported over the twisted-pair cable, wherein the high-speed data services include at least uncompressed multimedia data, Ethernet data, and Universal Serial Bus data.

Abstract: Disclosed are improved methods, systems, and computer program products for implementing an interface for visualizing, generating, and optimizing an I/O ring arrangement for an electronic design. A ribbon-based interface may be employed to visually see and control the design of the I/O ring.

Abstract: In one embodiment of the invention, a method of physical clock topology planning for designing integrated circuits is disclosed. The method includes reading an initial placed netlist of an integrated circuit design and a floorplan of the integrated circuit design, analyzing the integrated circuit design to determine potential enable signals to gate clock signals that clock the plurality of flip flops to reduce power consumption; simultaneously optimizing and placing the clock enable logic gates to gate clock signals to the plurality of flip flops; and minimizing timing variation of the clock signals to the plurality of flip flops.

Abstract: A system and method for synchronizing the display and edit of a plurality of connected layouts or documents within a single display. A first document or plurality of elements may be displayed as active and a second document or plurality of elements may be displayed as non-active background in a first window. The second document or plurality of elements may be displayed as active and the first document or plurality of elements may be displayed as non-active background in a second window. Any action detected in either window may be displayed in the other window. Upon selection of any active element or predefined net list, the elements physically or logically connected to the selected element or net list may be highlighted in the active documents, listed, or otherwise identified. An inter-document net list may identify connections between existing net lists in multiple documents.

Abstract: Systems, apparatus, and methods of static timing analysis for an integrated circuit design in the presence of noise are disclosed. The integrated circuit design may be partitioned into a plurality of circuit stages. A timing graph including timing arcs is constructed to represent the timing delays in circuit stages of the integrated circuit design. A model of each circuit stage may be formed including a model of a victim driver, an aggressor driver, a victim receiver, and a victim net and an aggressor net coupled together. For each timing arc in the timing graph, full timing delays may be computed for the timing arcs in each circuit stage.

Abstract: A system, method, and computer program product for using continuous parameter value updates to rapidly evaluate parameterized cells in a design tool. Embodiments display parameters and corresponding parameter values of parameterized cells in a circuit design in a GUI, adjust parameter values according to user input, evaluate the parameterized cell, and present results of the evaluating in the GUI during the displaying. Parameters influence circuit layout, circuit schematics, or simulation settings. Parameter values include current, minimum, maximum, and increment values. Parameterized cells may be individual cell instances, submaster cells, or master cells. Embodiments integrate validation tools and detect design rule check violations, assertion violations, invalid parameter values, and evaluation errors, and responsively generate user error alerts and selectively disallow further adjusting. Embodiments generate test circuits, each using a parameter value from a permutation of the adjusted parameter values.

Abstract: A method and system are provided for maintaining dynamic visual cues/graphic indicia for associated circuitry of a schematic object. The dynamic visual cues or graphic indicia indicate a number of states of the parent circuit object and its associated circuitry. The visibility, placement status, and other attributes of the parent or associated circuitry may be quickly discerned by inspection of the visual indicia. Navigation, including manipulations of one or both of the parent and associated circuitry are available through actuation of the visual cue or a selectable button proximately disposed thereto.

Abstract: Methods and systems provide a memory cell and a memory cell system for data serialization. In an embodiment, a half-rate serialization procedure uses a half-rate differential clock to output full-rate serial data. In an embodiment, the memory cell system includes two memory cells each receiving a respective data stream. Each memory cell may be controlled by a respective clock, the clocks being substantially mutually exclusive such that the output of each memory cell becomes alternately tri-stated. Based on the principle of a transistor tri-state or hold mode, if clocks of two memory cells are substantially mutually exclusive, then a tri-stated node can be driven by either of the memory cells in a substantially mutually exclusive manner, effectively multiplexing input parallel data to output serial data. The memory cell system may include a combination of different types of memory cells.

Abstract: A system and method for preventing an application program, which is licensed to a customer to be exclusively executed in a processor based on a certain processor design, from being executed properly in unauthorized processors is provided. The system includes a scrambling module and a recovery module. The scrambling module scrambles a selected portion of the application program using an identifier which identifies the authorized processor design. The recovery module adds an unscrambling program to the application program such that when the program is running in a processor, it retrieves a second identifier from the processor and unscrambles the scrambled portion of the application program using the retrieved second identifier. If the second identifier does not correspond to an authorized processor design, the unscrambling operation will incorrectly unscramble the scrambled portion and the application program will not run properly.

Abstract: Some aspects enable users to interactively define a region in an electronic design, identify or generate a track pattern, and assign the track pattern to the region for subsequent physical implementation for the region. Another aspect interactively represents various results on a display apparatus using one or more distinguishing representation schemes. Another aspect is directed at interactive editing a component of an electronic design having track patterns by iteratively modifying a set of track patterns to reach a reduced set of track patterns and by automatically snapping the component to active track(s) in the reduced set for the physical implementation.

Abstract: A programmable intellectual property block includes a PWM processor core to perform audio processing on input audio signals with firmware-driven modules to generate PWM output samples without using digital-analog converters or application processors. PWM processor core directly writes PWM output samples to queues of PWM peripherals to generate and transmit PWM digital pulses used by power stage(s) to drive electroacoustic transducers. Audio processing module(s) and PWM processing module(s) are implemented as a part of the firmware stored on the programmable processor core and are co-optimized by accessing the firmware. PWM processor core is dynamically configurable by identifying appropriate modules or information from the firmware based at least in part upon optimization objectives.

Abstract: Systems and method for automatically generating a set of shared processor datapaths from the description of the behavior of one or more ISA operations is presented. The operations may include, for example, the standard operations of a processor necessary to support an application language such as C or C++ on the ISA. Such operations, for example, may represent a configurable processor ISA. The operations may also include one or more extension operations defined by one or more designers. Thus, a description of the behaviors of the various standard and/or extension operations that compose the ISA of an instance of a standard or configurable processor is used to automatically generate a set of shared processor datapaths that implement the behavior of those operations.

Abstract: Disclosed are methods, systems, and articles of manufacture for assigning track patterns to regions of an electronic design in one or more embodiments. One aspect tessellates an area on a layer of an electronic design that is subject to one or more track pattern requirements and dynamically maintains the tessellation structure from the tessellation process for early stages of the design process such as floorplanning, placement, or routing. Another aspect identifies or creates multiple strips or multiple regions for an area on a layer of an electronic design and assigns or associates a track pattern or a track pattern group to each of the multiple strips or multiple regions. In this latter aspect, a track pattern or a track pattern group is no longer required to apply to the entire layer.

Abstract: Disclosed are methods, systems, and articles of manufactures for implementing a physical design with force directed placement or floorplanning and layout decomposition by identifying multiple nodes and then iteratively generating multiple cells by using the multiple nodes in a decomposition process and applying force model(s) to iteratively morph the cells until convergence criteria are satisfied to generate a layout or floorplan of an electronic design without requiring complete conductivity for the electronic design. The initially identified custom conductivity information is maintained throughout this iterative process.

Abstract: The present disclosure relates to a method for verifying a digital design using a computing device. The method may include determining one or more tests associated with verifying the digital design and generating, using the computing device, a verification result by performing one or more verification runs on the digital design. The method may further include merging coverage data generated by the one or more verification runs and ranking the one or more tests based upon, at least in part, a first verification run having a first configuration and a second verification run having a second configuration, wherein the first and second configurations differ.

Abstract: A method including accessing a first virtual prototype configured to perform a first simulation of a hardware design, identifying checkpoints within the first virtual prototype, each checkpoint including a storage state and/or behavioral state, and determining breakpoints for dividing execution of a second virtual prototype into a series of execution segments, where the second virtual prototype is configured to perform a second simulation of the hardware design, the second virtual prototype includes virtual models representing a separate portion of the hardware design, each virtual model representing a same portion of the hardware design as a corresponding virtual model of the first virtual prototype.

Abstract: A system and method is described in which the state of the art in automated software applications is significantly improved. According to some approaches, interface testing is implemented and based upon a verification language and a verification environment. The system and method support the concepts of constrained random test generation, coverage, constrained random generation, and dynamic checks.

Abstract: A version management system for fluid guard ring (FGR) PCells uses one or more new version management parameters that are added to the FGR PCell definition to manage the source code versions for a PCell. The system saves instance layout information with a version management parameter that identifies the current PCell source code version for each FGR PCell instance. When evaluated using a newer version of the PCell source code, the instance layout information generated with a previous version of PCell source code can be retrieved. The retrieved layout information will be used during evaluation of the PCell to ensure the integrity of the PCell geometries that were previously verified. The saved layout information will be uniquely identifiable with a hash code of the name-value pairs for one or more parameters associated with the PCell instance.

Abstract: An approach is described for implementing a GUI that an account for illegal operations by the user. Visual ghosting is implemented that includes separation support. If an object is manipulated into an impermissible/unacceptable configuration, ghosting separation is performed to display multiple ghost images, where a first ghost image shows a legal configuration of the object and a second ghost image shows the current configuration of the object. The second ghost continues to track the user's manipulation of the object until a legal configuration is achieved. The improved approach provides a visual representation that corresponds to the expected end result, but is also be useful to track the user's actions if there is a violation.

Abstract: Disclosed are methods, systems, and articles of manufactures for implementing multiple-patterning-aware design rule check for an electronic design. Various embodiments identify one or more sets of multiple-exposure grids and identify or generate a data structure by using the one or more sets of grids to store design data of shape ends of various ends. Various embodiments perform constant time design rule checking by performing a constant time search process on the data structure to look up from the data structure one or more violations of one or more design rules which include at least one directional design rule. Some aspects are directed at fixing a design rule violation by using at least some grids of the one or more sets of grids.