Patents Assigned to Design Technology, Inc.
  • Publication number: 20110155419
    Abstract: A cable exhibiting reduced crosstalk between transmission media includes a core having a profile with a shape which defines spaces or channels to maintain a spacing between transmission media in a finished cable. The core is formed of a conductive material to further reduce crosstalk. A method of producing a cable introduces a core as described above into the cable assembly and imparts a cable closing twist to the assembly.
    Type: Application
    Filed: May 5, 2003
    Publication date: June 30, 2011
    Applicant: Cable Design Technologies Inc. dba Mohawk/CDT
    Inventors: William T. Clark, Peter D. McDonald, Joseph Dellagala
  • Publication number: 20110087262
    Abstract: The method for making a reinforced balloon for a balloon catheter involves blending a polymer with a nano composite to form a composite matrix, extruding a parison from the composite matrix, blow molding the parison into a balloon and orienting the nano composite generally axially with respect to the balloon. The balloon formed has a high strength for resisting bursting. The nano composite may be carbon nanotubes, nano-ceramic fibers or a nano clay.
    Type: Application
    Filed: December 20, 2010
    Publication date: April 14, 2011
    Applicant: MICRUS DESIGN TECHNOLOGY, INC.
    Inventor: Oscar Jimenez
  • Patent number: 7905877
    Abstract: The intravascular catheter has two segments; a proximal segment with high stiffness and a distal segment with lower stiffness. The catheter can also have an intermediate segment of lower stiffness than the proximal segment and higher stiffness than the distal segment. The catheter comprises a polymeric inner tube, a reinforcing inner jacket which is spirally wound over the inner tube and which becomes progressively softer from a proximal end to a distal end, and a polymeric outer sheath extruded over the inner jacket according to the teachings of U.S. Pat. No. 5,445,624. The reinforcing jacket comprises helical coiled wires or fibers of various materials and layers wound over the inner tube in order to provide improved multi-axial mechanical properties, such as torque, compression, tension and anti-kinking characteristics.
    Type: Grant
    Filed: May 12, 2006
    Date of Patent: March 15, 2011
    Assignee: Micrus Design Technology, Inc.
    Inventors: Oscar Jimenez, Roberto Echarri, Kenneth Verduin
  • Publication number: 20090129091
    Abstract: A filter for a fluorescent lighting tube. The filter includes a sheet of polymeric material having fold lines scribed thereon, defining a plurality of sections. The sections allow the filter to be positioned about and secured to a fluorescent tube without removal of the tube from its mounting fixture. The filter of the may be configured to filter color, ultraviolet light, or other wavelengths of the electromagnetic spectrum.
    Type: Application
    Filed: November 14, 2008
    Publication date: May 21, 2009
    Applicant: APOLLO DESIGN TECHNOLOGY, INC.
    Inventors: Jeff Mateer, Jason C. Kabot
  • Publication number: 20090066843
    Abstract: A color mixer for producing a colored beam of light in combination with a light source. The color mixer includes a plurality of color media configured to pass a light beam such that the color media may be repositioned relative to one another to produce a color mixing effect resulting in many available combinations of color and hue.
    Type: Application
    Filed: September 8, 2008
    Publication date: March 12, 2009
    Applicant: APOLLO DESIGN TECHNOLOGY, INC.
    Inventors: Jeff Mateer, Keersten Nichols, Michael Wood
  • Patent number: 7483820
    Abstract: In one embodiment, a method for ranking webpages is provided. The method includes generating a web circuit model having a node representing each webpage. The model is simulated to identify the potential at each node. The webpages can then be ranked according to the potentials of the nodes to which the webpages correspond.
    Type: Grant
    Filed: April 17, 2007
    Date of Patent: January 27, 2009
    Assignee: Gemini Design Technology, Inc.
    Inventor: Baolin Yang
  • Patent number: 7287340
    Abstract: The present invention provides soles, platforms, or inserts incorporated into footwear, preferably athletic footwear, designed to promote a more efficient running technique by an energy-translating sole comprising one or more angular displacement members, balance-thrust members, and counterbalance as well as conventional features. Systems and methods of the present invention promote more efficient running technique by facilitating foot-strike to occur at a point under and behind the runner's center of gravity. This may be accomplished, for example, by a foot-strike member, angular displacement member and balance-thrust member working cooperatively to displace the runner's center of gravity and translate gravitational, inertial and ground reaction forces, as well as muscular tension forces, into linear momentum.
    Type: Grant
    Filed: May 18, 2004
    Date of Patent: October 30, 2007
    Assignee: Sydney Design Technologies, Inc.
    Inventor: Daniel Talbott
  • Patent number: 7231336
    Abstract: In accordance with the present invention there is provided a method for performing a glitch check in simulating a circuit. Current maximum and minimum values for optimization parameters of the circuit are determined. Next, a signal pulse characteristic for the circuit simulation is determined based on the maximum and minimum optimization parameters. A current averaged optimization parameter is determined from the current maximum and minimum optimization parameters. A prime criterion parameter is calculated based on the optimization parameters and the signal pulse characteristic value. If the prime criterion parameter converges into a specified range then measurement results from the circuit simulation are parsed and reported as final. If the prime criterion parameter does not converge, then the process continues by recalculating the optimization parameters until the prime criterion parameter converges.
    Type: Grant
    Filed: December 5, 2003
    Date of Patent: June 12, 2007
    Assignee: Legend Design Technology, Inc.
    Inventors: You-Pang Wei, Yuhung Liao, Mingchi Liu, YuJiao Ping
  • Patent number: 7203918
    Abstract: A method for performing a signal integrity and delay check for circuit simulations is disclosed. Nodes of the circuit are selected and an optimization parameter is determined. The optimization parameter may be either the setup or hold time for the circuit simulation. The current optimization parameter is determined to be the average of the current minimum and maximum optimization parameters. A primary criteria is calculated in response to the optimization parameters. The primary criteria may be a bisection error of the circuit simulation. If the primary criteria converges to a prescribed range, then the measurement results from the simulation are parsed. If the primary criteria does not converge, then the circuit is simulated using the current optimization parameter. For a signal integrity check, switch difference errors are identified and used to set a new optimization parameter. For a delay check, delay difference errors are identified and used to set a new optimization parameter.
    Type: Grant
    Filed: November 4, 2004
    Date of Patent: April 10, 2007
    Assignee: Legend Design Technology, Inc.
    Inventors: You-Pang Wei, George (Yuhung) Liao, Mickie (Mingchi) Liu, Yu-Jiao Ping
  • Patent number: 7131088
    Abstract: In accordance with the present invention there is provided a method for determining an optimized parameter for a circuit simulation. A circuit path for the simulation is determined, and maximum and minimum optimization parameters are decided. Next, the circuit path is simulated using the maximum optimization parameter. The circuit path is simulated using the minimum optimization parameter and a primary criteria parameter is also calculated. The simulations are compared to determine whether the same status (both succeed or both fail) is generated for both the minimum optimization parameter and the maximum optimization parameter. If the simulations do not indicate the same status, then the optimization parameter is recalculated and the circuit is simulated until the primary criteria parameter converges to a prescribed value.
    Type: Grant
    Filed: December 5, 2003
    Date of Patent: October 31, 2006
    Assignee: Legend Design Technology, Inc.
    Inventors: You-Pang Wei, Yuhung Liao, Mingchi Liu, YuJiao Ping
  • Publication number: 20060169478
    Abstract: A multi-pair cable including a plurality of twisted pairs of insulated conductors, including first and second twisted pairs, each having a closing lay length (twist lay length measured after the twisted pairs are cabled together with a particular cable lay) of less than about 0.6 inches, the plurality of twisted pairs being twisted together with a cable lay of greater than about three inches to form the cable. In some examples, the multi-pair cable may further comprise a separator disposed between the first and second twisted pairs. In another example, a ratio between a longest closing lay length and a shortest closing lay length in the cable is less than 1.65 inches. In another example, the cable further includes at least one additional twisted pair of conductors having a closing lay length that is greater than about 0.6 inches, and the cable lay length is less than about four inches.
    Type: Application
    Filed: January 28, 2005
    Publication date: August 3, 2006
    Applicant: Cable Design Technologies, Inc.
    Inventor: William Clark
  • Publication number: 20060161413
    Abstract: A method for simulating large circuits in full-scale. To enhance the simulation efficiency, subcircuits are extracted from a circuit and thence a hierarchical structure is established using the extracted subcircuits. Subsequently, the circuit is partitioned and a current-voltage table for each subcircuit is dynamically generated. A transient analysis of the circuit is preformed at each incremental time step and a recursive latency check is preformed from the top to the bottom level of the hierarchical structure to determine the active part of the circuit. Using the current-voltage curves, a portion of the conductance matrix corresponding to the active part is rebuild at each incremental time step, which significantly reduces the simulation time.
    Type: Application
    Filed: January 13, 2006
    Publication date: July 20, 2006
    Applicant: Legend Design Technology, Inc.
    Inventors: You-Pang Wei, Heng-Liang Huang, Scott (Shih-Chia) Lin, Hung-Ta Wei, Adrian Wen, Shu Wu
  • Publication number: 20050120317
    Abstract: A method for performing a signal integrity and delay check for circuit simulations is disclosed. Nodes of the circuit are selected and an optimization parameter is determined. The optimization parameter may be either the setup or hold time for the circuit simulation. The current optimization parameter is determined to be the average of the current minimum and maximum optimization parameters. A primary criteria is calculated in response to the optimization parameters. The primary criteria may be a bisection error of the circuit simulation. If the primary criteria converges to a prescribed range, then the measurement results from the simulation are parsed. If the primary criteria does not converge, then the circuit is simulated using the current optimization parameter. For a signal integrity check, switch difference errors are identified and used to set a new optimization parameter. For a delay check, delay difference errors are identified and used to set a new optimization parameter.
    Type: Application
    Filed: November 4, 2004
    Publication date: June 2, 2005
    Applicant: Legend Design Technology, Inc.
    Inventors: You-Pang Wei, George (Yuhung) Liao, Mickie (Mingchi) Liu, Yu-Jiao Ping
  • Publication number: 20050049844
    Abstract: In accordance with the present invention there is provided a method for performing a glitch check in simulating a circuit. Current maximum and minimum values for optimization parameters of the circuit are determined. Next, a signal pulse characteristic for the circuit simulation is determined based on the maximum and minimum optimization parameters. A current averaged optimization parameter is determined from the current maximum and minimum optimization parameters. A prime criterion parameter is calculated based on the optimization parameters and the signal pulse characteristic value. If the prime criterion parameter converges into a specified range then measurement results from the circuit simulation are parsed and reported as final. If the prime criterion parameter does not converge, then the process continues by recalculating the optimization parameters until the prime criterion parameter converges.
    Type: Application
    Filed: December 5, 2003
    Publication date: March 3, 2005
    Applicant: Legend Design Technology, Inc.
    Inventors: You-Pang Wei, Yuhung Liao, Mingchi Liu, YuJiao Ping
  • Publication number: 20050050498
    Abstract: In accordance with the present invention there is provided a method for determining an optimized parameter for a circuit simulation. A circuit path for the simulation is determined, and maximum and minimum optimization parameters are decided. Next, the circuit path is simulated using the maximum optimization parameter. The circuit path is simulated using the minimum optimization parameter and a primary criteria parameter is also calculated. The simulations are compared to determine whether the same status (both succeed or both fail) is generated for both the minimum optimization parameter and the maximum optimization parameter. If the simulations do not indicate the same status, then the optimization parameter is recalculated and the circuit is simulated until the primary criteria parameter converges to a prescribed value.
    Type: Application
    Filed: December 5, 2003
    Publication date: March 3, 2005
    Applicant: Legend Design Technology, Inc.
    Inventors: You-Pang Wei, Yuhung Liao, Mingchi Liu, YuJiao Ping
  • Publication number: 20050049845
    Abstract: In accordance with the present invention there is provided a method of simulating a memory circuit design in order to verify the signal strength of bit lines. The method begins by identifying circuit elements of the memory circuit design. Next, a memory circuit path is extracted from the circuit elements. The memory circuit is simulated and the maximum voltage difference between bit lines is measured. The maximum voltage difference is measured to a noise margin in order to verify the signal strength of the bit lines.
    Type: Application
    Filed: December 5, 2003
    Publication date: March 3, 2005
    Applicant: Legend Design Technology, Inc.
    Inventors: You-Pang Wei, Yuhung Liao, Mingchi Liu, YuJiao Ping
  • Publication number: 20050049846
    Abstract: There is provided a method of performing a timing soft error check on a simulated circuit. The method comprises creating a critical-path circuit or using a full-chip circuit to be analyzed of the circuit. Next, the circuit is simulated based on an initial minimum optimization parameter and an initial maximum optimization parameter. A maximum and minimum primary criterion parameter are calculated for each of the minimum and maximum optimization parameters. If the minimum and maximum optimization parameters do not indicate the same status (i.e., both succeed or both fail), then a new current optimization parameter is determined. The circuit is then simulated using the new current optimization parameter. If the simulation is successful, then a timing soft error check is performed. If the simulation is not successful, then it is determined if the primary criterion parameter is converging. If the primary criterion parameter is not converging, then the current optimization parameter is set to a new value.
    Type: Application
    Filed: December 5, 2003
    Publication date: March 3, 2005
    Applicant: Legend Design Technology, Inc.
    Inventors: You-Pang Wei, Yuhung Liao, Mingchi Liu, YuJiao Ping
  • Publication number: 20050006132
    Abstract: Cables including a plurality of twisted pairs of insulated conductors and a core disposed between the plurality of twisted pairs of insulated conductors so as to separate at least one of the plurality of twisted pairs of insulated conductors from others of the plurality of twisted pairs of insulated conductors. In one example, a cable may include a jacket having a plurality of protrusions. In another example, the core may include one or more pinch points to facilitate breaking of the core. In yet another example, two or more cables may be bundled, and possibly twisted, together to form a bundled cable.
    Type: Application
    Filed: November 10, 2003
    Publication date: January 13, 2005
    Applicant: Cable Design Technologies Inc., dba Mohawk/CDT
    Inventor: William Clark
  • Patent number: 6812408
    Abstract: An improved data telecommunications cable includes a plurality of twisted pairs of insulated conductors and at least one configurable tape separator disposed between the plurality of twisted pairs of insulated conductors along a longitudinal length of the cable. The communications cable also includes a jacket assembly enclosing the plurality of twisted pairs of insulated conductors and the configurable tape separator. The configurable tape separator separates at least one of the plurality of twisted pairs of insulated conductors from others of the plurality of twisted pairs of insulated conductors with a spacing sufficient to provide a desired crosstalk isolation between each of the plurality of twisted pairs of insulated conductors. The configurable tape separator may include a dielectric tape and one or more conductive or partially conductive layers.
    Type: Grant
    Filed: May 28, 2003
    Date of Patent: November 2, 2004
    Assignee: Cable Design Technologies, Inc.
    Inventors: William Clark, Joseph Dellagala, Kenneth Consalvo
  • Publication number: 20040205983
    Abstract: The present invention provides soles, platforms, or inserts incorporated into footwear, preferably athletic footwear, designed to promote a more efficient running technique by an energy-translating sole comprising one or more angular displacement members, balance-thrust members, and counterbalance as well as conventional features. Systems and methods of the present invention promote more efficient running technique by facilitating foot-strike to occur at a point under and behind the runner's center of gravity. This may be accomplished, for example, by a foot-strike member, angular displacement member and balance-thrust member working cooperatively to displace the runner's center of gravity and translate gravitational, inertial and ground reaction forces, as well as muscular tension forces, into linear momentum.
    Type: Application
    Filed: May 18, 2004
    Publication date: October 21, 2004
    Applicant: Sydney Design Technologies, Inc.
    Inventor: Daniel Talbott