Abstract: Provided in the present invention are a high speed and low program voltage nonvolatile memory cell, a programming method for same and a nonvolatile memory array. A nonvolatile memory cell comprises a first gate insulator formed on a surface of a first channel forming semiconductor region adjacent to a source region; a second gate insulator formed on a surface of a second channel forming semiconductor region adjacent to a drain region; a first gate electrode formed on said first gate insulator; and a second gate electrode formed on said second gate insulator wherein the second gate insulator includes a first layer forming a potential barrier at the interface with the second channel forming region; a third layer forming a potential barrier at the interface with the second gate electrode and the second layer between the first and third layers forming a carrier trapping level.

Abstract: An fast program, ultra-high density, dual-bit, multi-level flash memory process, which can be applied to a ballistic step split gate side wall transistor, or to a ballistic planar split gate side wall transistor, which enables program operation by low voltage requirement on the floating gate during program is described. Two side wall floating gates are paired with a single word line select gate, and word lines are arranged to be perpendicular both the bit lines and control gate lines. Two adjacent memory cells on the same word line do not require an isolation region. Also, the isolation region between adjacent memory cells sharing the same bitline is defined by the minimum lithography feature, utilizing a self align fill technique. Adjacent memory cells on the same word line share bitline diffusion as well as a third poly control gate. Control gates allow program and read access to the individual floating gate.

Abstract: An fast program, ultra-high density, dual-bit, multi-level flash memory process, which can be applied to a ballistic step split gate side wall transistor, or to a ballistic planar split gate side wall transistor, which enables program operation by low voltage requirement on the floating gate during program is described. Two side wall floating gates are paired with a single word line select gate, and word lines are arranged to be perpendicular both the bit lines and control gate lines. Two adjacent memory cells on the same word line do not require an isolation region. Also, the isolation region between adjacent memory cells sharing the same bitline is defined by the minimum lithography feature, utilizing a self align fill technique. Adjacent memory cells on the same word line share bitline diffusion as well as a third poly control gate. Control gates allow program and read access to the individual floating gate.

Abstract: In the present invention a nonvolatile memory array architecture can be realized by a fabrication process more compatible to an MOS logic fabrication process as compared with previous nonvolatile memory array architectures. Higher write and/or read speed is possible because of a lower bit line resistance. A high hard bit density near 4F2 is possible when a self-align contact technology and a border less contact technology are used. Connection regions are formed throughout the memory array comprising four cells that are connected to one bit line. The connection regions can be formed in the same processing step with opposite conductivity regions for economy of processing. A plurality of memory cells are two dimensionally disposed in two different directions with connection regions, conductive bit lines extending in the first direction, conductive word lines extending in the second direction, and conductive control lines.

Abstract: A wordline decoder for high density flash memory is described with negative voltage capability for memory operations such as erase. A main decoder is shared with a plurality of wordline driver circuits to reduce wiring congestion and overall layout size. In a second embodiment a wordline decoder for fast read access is provided in which a high speed positive voltage decoder is separate from the negative voltage decoder with the addition of a triple well NMOS transistor into the inverter driver circuits. The use of triple well NMOS transistors reduces circuit and layout complexity.

Abstract: A telecommunications cable is disclosed in which a plurality of inwardly extending projections from the cable jacket, form a first and second plurality of substantially parallel longitudinal channels within the cable jacket. The first and second plurality of longitudinal channels are spaced apart from one another with respect to a reference line that transverses the cable, wherein the plurality of inwardly extending projections provide the spaced apart distance between the first plurality and the second plurality of longitudinally extending channels and between corresponding transmission media disposed within the first and second plurality of longitudinally extending channels. With this arrangement, cross talk between the transmission media within the cable is reduced and alien crosstalk between adjacently disposed or stacked cables is also reduced.

Abstract: A process is provided for generating a synoptic layout database for efficient layout parasitic extraction and circuit simulation in post-layout verification of an integrated circuit (IC) design for a system having a plurality of repetitive subcircuits. The process includes the steps of: receiving an input layout database including a plurality of geometric objects including cells representing the IC design, each of the cells including a plurality of polygons; identifying a plurality of repetitive cells of the input layout database, the repetitive cells being associated with the repetitive sub-circuits; recognizing at least one pattern of the repetitive cells; defining at least one cut region of the input layout database, the cut region being defined by physical layout coordinates, the cut region intersecting a corresponding pattern of the repetitive cells; and generating a synoptic layout database.

Abstract: A method for making cable of at least two thermoplastic insulated electrical conductors by thermal bonding. Two electrical conductors are moved into an extruder and are coated independently with heated thermoplastic insulation which maintains concentricity of each conductor with respect to the surrounding insulation. The insulated conductors are held in a spaced relationship until the insulation sets and then the heated insulated conductors are touched together causing the heated insulation to fuse together thereby joining them.

Abstract: An automatic memory characterization system for determining timing characteristics associated with each of a plurality of circuit instances of a memory compiler circuit design includes: an automatic circuit reduction tool for receiving a circuit netlist extracted from layout data defining a circuit instance of the memory compiler, and for generating a critical path netlist; a memory storage unit for storing a timing parameter database including a script file having memory characterization instructions, and at least one specification file associated with one of the timing characteristics to be characterized for the circuit instance, the specification file having a plurality of input signal parameters defining a plurality of input signals to be applied to selected input nodes of the circuit instance, and a plurality of output loading parameters defining a plurality of output loads to be applied to selected output nodes of the circuit instance; a stimulus generator responsive to the input signal parameters and o

Abstract: An improved data telecommunications cable according to the invention includes a plurality of twisted pairs of insulated conductors, and a dielectric pair separator formed with a plurality of folds, to provide a plurality of grooves extending along a longitudinal length of the dielectric filler. Each twisted pair of insulated conductors is disposed within a groove of the dielectric pair separator. The data communications cable also includes a jacket assembly enclosing the plurality of twisted pairs of insulated conductors and the dielectric pair separator. The dielectric pair separator separates each twisted pair of insulated conductors from every other twisted pair of insulated conductors with a spacing sufficient to provide a desired crosstalk isolation between each of the plurality of twisted pairs of insulated conductors.

Abstract: A telecommunications cable is disclosed in which a plurality of inwardly extending projections from the cable jacket, form a first and second plurality of substantially parallel longitudinal channels within the cable jacket. The first and second plurality of longitudinal channels are spaced apart from one another with respect to a reference line that transverses the cable, wherein the plurality of inwardly extending projections provide the spaced apart distance between the first plurality and the second plurality of longitudinally extending channels and between corresponding transmission media disposed within the first and second plurality of longitudinally extending channels. With this arrangement, cross talk between the transmission media within the cable is reduced and alien crosstalk between adjacently disposed or stacked cables is also reduced.

Abstract: A method for identifying and selecting pertinent subcircuits from a given circuit design for generating simulation results representative of the given circuit design is disclosed. A large circuit design having a number of input pins and output pins, and one or more clock pins can be simulated by a number of subcircuits where each subcircuit is comprised of circuit information from an input pin to one or more latch devices, an output pin to one or more latch devices, or an output pin to one or more input pins. A latch device can be a flip-flop.

Abstract: A cable exhibiting reduced crosstalk between transmission media includes a core having a profile with a shape which defines spaces or channels to maintain a spacing between transmission media in a finished cable. The core is formed of a conductive material to further reduce crosstalk. A method of producing a cable introduces a core as described above into the cable assembly and imparts a cable closing twist to the assembly.

Abstract: A communication cable includes at least a first and a second twisted pairs of conductors. The first twisted pair of conductors is covered by a first insulation material, and the second twisted pair of conductors is covered by a second insulation material that is different than the first insulation material. The second twisted pair of conductors has a signal phase delay that is substantially equal to the signal phase delay of the first twisted pair of conductors such that the skew of the cable is substantially zero. In certain embodiments, the first insulation material is a fluoropolymer. In such embodiments, the second insulation material may be a nonfluoropolymer. In addition, the twist lay of the first twisted pair of conductors may be different than the twist lay of the second twisted pair of conductors. Moreover, the thickness of the first insulation material may be different than the thickness of the second insulation material.

Abstract: A layout parasitic extraction system. The present invention is a connectivity-based approach for extracting layout parasitics. The present invention creates a connectivity-based database, where geometries of a layout are organized by net. The present invention allows net-by-net extraction of layout parasitics using a connectivity-based database. Furthermore, a user can select a net or nets for extraction. The present invention outputs a database containing nets and their extracted layout parasitics. The present invention can create a netlist format file from a database containing nets and their extracted parasitics to allow back annotation of layout parasitics into a circuit schematic or for use for other software (possibly from a third-party).

Abstract: A high-speed data communications cable has geometrically concentric layers of twisted pairs of wires. A first, innermost layer includes a first twisted pair of wires having a unique lay length and a first and second dielectric filler. A second geometrically concentric layer is formed about the innermost layer and includes 9 twisted pairs of wires having 5 lay lengths. A third geometrically concentric layer is formed about the second layer and includes 25 twisted pairs of wires having 5 lay lengths. The first, second and third layers are enclosed in a thermoplastic jacket resulting in a flexible data cable with a minimal diameter. Additional layers of more twisted pairs of wires may also be used. A plurality of communication cables may also be commonly sheathed.

Abstract: An engine has a pair of rotors, both housed within the same housing. The housing has an interior cavity which is preferably spherical but need only be partially spherical, the remainder at least having rotational symmetry. Each rotor is mounted on an axis that passes through the center of the cavity, the respective axes of the rotors being at an angle to each other, with the center of each rotor being at the center of the cavity. The rotors interlock with each other to define chambers. Vanes or pistons defined by a contact face and a side face protrude from the rotors. The side faces and contact faces, and the housing interior define chambers that open and close as the rotors rotate. Each contact face of one rotor is defined by the rotation of a conical section of material on the other rotor, so that there is constant linear contact between opposing vanes on the two rotors, at least on one side of the engine. The rotors may face each other or be one inside the other.

Abstract: A method and apparatus for producing a thermoplastic container-shaped intermediate or article having biaxially oriented side walls and a bottom having an unoriented portion surrounded by a biaxially oriented transparent portion. In the method, a sheet of thermoplastic at its orientation temperature is secured over the mouth of a forming tube. A plunger having a circumscribing sharp edged lip and a plunger follower sandwich the thermoplastic sheet and the plunger and plunger follower are driven into the forming tube while preventing the circumscribed portion of the thermoplastic from becoming oriented. Thereafter the thermoplastic is blow formed to yield a container-shaped intermediate. The final container is formed by heat shrinking the intermediate onto a male form having a predetermined size, shape and texture. The apparatus includes the forming tube, plunger, plunger follower and pressurized air for performing the method.

Abstract: A rear suspension system for a bicycle. The system directs the rear wheel along a predetermined, S-shaped path as the suspension is compressed. The path is configured to provide a chainstay lengthening effect only at those points where this is needed to counterbalance the pedal inputs of the rider; at those points in the wheel travel path where there is a chainstay lengthening effect, the chain tension which results from the pedal inputs exerts a downward force on the rear wheel, preventing unwanted compression of the suspension. The system employs a dual eccentric crank mechanism mounted adjacent the bottom bracket shell to provide the desired control characteristics.