Abstract: The present invention includes a twisted pair cable having a plurality of pairs, wherein each has two conductors. Each of the conductors is covered with an inner layer insulator and an outer layer insulator, wherein the positioning of the conductors within the inner and outer insulators is eccentric with respect to the inner and outer insulators. This invention also includes a method of making a cable of the same configuration.

Abstract: A storage package for a recording medium having a first frame component having at least one side and a first engagement end and a second frame component having at least one side and a second engagement end, each of the first and second frame components configured to hingedly engage each other and at least one of the first and second frame components having at least one side that receives a blank. The blank includes a plurality of generally planar panels defined by scores which can be slidably inserted into at least one of the receiving portions of the frame components. When the blank is inserted into the first and the second frame components in an engaged position, an enclosable space for placement of a recording medium is formed.

Abstract: A storage package for a recording medium having a first frame component having at least one side and a first engagement end and a second frame component having at least one side and a second engagement end, each of the first and second frame components configured to hingedly engage each other and at least one of the first and second frame components having at least one side that receives a blank. The blank includes of a plurality of generally planar panels defined by scores which can be slidably inserted into at least one of the receiving portions of the frame components. When the blank is inserted into the first and the second frame components in an engaged position, an enclosable space for placement of a recording medium is formed.

Abstract: An improved data telecommunications cable according to the invention includes a plurality of twisted pairs of insulated conductors, and a substantially flat configurable dielectric separator disposed between the plurality of twisted pairs of insulated conductors along a longitudinal length of the telecommunications cable. The data communications cable also includes a jacket assembly enclosing the plurality of twisted pairs of insulated conductors and the substantially flat dielectric pair separator. The substantially flat dielectric pair separator separates each twisted pair of insulated conductors from every other twisted pair of insulated conductors with a spacing sufficient to provide a desired crosstalk isolation between each of the plurality of twisted pairs of insulated conductors.

Abstract: A cable exhibiting reduced crosstalk between transmission media includes a core having a profile with a shape which defines spaces or channels to maintain a spacing between transmission media in a finished cable. The core is formed of a conductive material to further reduce crosstalk. A method of producing a cable introduces a core as described above into the cable assembly and imparts a cable closing twist to the assembly.

Abstract: The present invention provides a unitary sliding-vane type compressor-expander comprising a housing with a compressor inlet and outlet, and an expander inlet and outlet. A single rotor is disposed therein defining in cooperation with the housing a compression chamber on one side and an expansion chamber on the opposite side. The rotor includes a plurality of regularly spaced vanes slidingly disposed in slots about the periphery of the rotor. The bottoms of the vane slots may be vented through a passage in the housing to the inlet air, or alternatively through a groove between the vane and vane slot to the compression or exhaust chambers. Permanent magnets are used in the vanes and housing to increase or decrease the contact force between the vane tip and housing. An integral condenser-humidifier is provided in the path of the expanded gas exhausting from the turbine outlet for condensing water out of the expanded gas and returning the condensed water to the compressor-expander.

Abstract: An improved data telecommunications cable according to the invention includes a plurality of twisted pairs of insulated conductors, and a dielectric pair separator formed with a plurality of folds, to provide a plurality of grooves extending along a longitudinal length of the dielectric filler. Each twisted pair of insulated conductors is disposed within a groove of the dielectric pair separator. The data communications cable also includes a jacket assembly enclosing the plurality of twisted pairs of insulated conductors and the dielectric pair separator. The dielectric pair separator separates each twisted pair of insulated conductors from every other twisted pair of insulated conductors with a spacing sufficient to provide a desired crosstalk isolation between each of the plurality of twisted pairs of insulated conductors.

Abstract: A system for changing a tool head (24) carried by a robot (20) includes a locking mechanism (23) having a keyhole-shaped slot (37) therein, and a lock key assembly (25) having a key (65). Depression of a button (52) rotates a cam arm (57) to extend the key (65) outwardly where it can be received in the larger opening (38) of the slot (37). Depression of the button (35) of the locking mechanism (23) moves the slot (37) such that the neck (68) of the key (65) is received in the smaller opening (39) of the slot (37). Release of the buttons (52, 35) then allows a spring (71) to retract the key (65) until its head (69) is received in a recess (40) of the locking mechanism (23) to attach the tool head (24) to the robot (20). The parts are detached by again depressing the button (52) which extends the key (65) to remove its head (69) from the recess (40) and then depressing a button (34) to move the slot (37) so that the key (65) is again in the larger opening (38) from where it may be removed.

Abstract: A cable bolt comprises a cable with a tubular yielding fixture at one of its ends. The pull-off load of such yielding fixture can be adjusted to a desired value. This is achieved by unwinding one end of the cable and inserting a slug over the kingwire. Then, the peripheral wires are wound again over the kingwire forming a bulge in the cable where the slug is located. The yielding fixture is then slid on the cable and forced over the bulged portion of the cable, while measuring the load required to achieve this operation, which also becomes the pull-off load of the yielding fixture. Finally, any part of the cable protruding from the fixture is cut-off to form the cable bolt with the desired yielding fixture at its end.

Abstract: A dual layer shielded electrical cable is disclosed. The cable has at least a pair of insulated conductors, a metallic shield and a jacket surrounding the shield and insulated conductors. A first jacket layer made of flame retardant material surrounds the insulated conductors. A metallic shield then surrounds the first jacket layer. A second jacket layer then surrounds and seals the metallic shield against the first jacket layer, such that the insertion of the first jacket layer provides the cable with electrical signal attenuation and impedance characteristics equivalent to that of an unshielded cable with similar conductor insulation thicknesses. In another embodiment, a dual layer plenum rated electrical cable is disclosed. The cable has at least a pair of insulated conductors and a jacket surrounding the insulated conductors. Both the first and second jacket layer are made of a low-smoke and flame-retardant materials.

Abstract: A dual layer shielded electrical cable is disclosed. The cable has at least a pair of insulated conductors, a metallic shield and a jacket surrounding the shield and insulated conductors. A first jacket layer made of flame retardant material surrounds the insulated conductors. A metallic shield then surrounds the first jacket layer. A second jacket layer then surrounds and seals the metallic shield against the first jacket layer, such that the insertion of the first jacket layer provides the cable with electrical signal attenuation and impedance characteristics equivalent to that of an unshielded cable with similar conductor insulation thicknesses. In another embodiment, a dual layer plenum rated electrical cable is disclosed. The cable has at least a pair of insulated conductors and a jacket surrounding the insulated conductors. Both the first and second jacket layer are made of a low-smoke and flame-retardant materials.

Abstract: The present invention provides a very compact, lightweight, turbomolecular pump for evacuating a chamber at volumetric flowrates of less than 10 liters per second. In one embodiment a turbomolecular pump is provided having a bladed rotor disposed within a housing, and mounted for rotation at one end on a passive magnetic main bearing and at the other end on a ball bearing. The pump is configured such that the magnetic bearing carries a majority of the rotor unbalance load. The rotor may be beneficially tapered from a larger diameter at the high vacuum end to a smaller diameter at the low vacuum end. The invention also provides a method of machining the blades of the rotor from a rotor blank using a single point tool in a two-step numerical control lathe operation. In another method of the invention, the rotor blades are individually cut using a high speed circular slitting saw by plunging the saw radially into the rotor blank.

Abstract: A system, an IC chip, a test structure formed on the IC chip, and a corresponding method for modeling one or more target interconnect capacitances is disclosed. The test structure comprises an interconnect configuration comprising a test interconnect and one or more target interconnects. The interconnect configuration has, for each target interconnect, a corresponding target interconnect capacitance between the test interconnect and the target interconnect. The test structure also comprises a test interconnect charging circuit connected to the test interconnect. The test interconnect charging circuit is configured to place a test charge on the test interconnect. The test structure further comprises one or more target interconnect charging circuits. Each target interconnect charging circuit is connected to a corresponding target interconnect.

Abstract: In the prior arts a twin MONOS memory erase is achieved by applying a positive bias to the bit diffusion and a negative bias to the control gate. The other word gate and substrate terminals are grounded. But the voltage of word gate channel adjacent to the control gate can dramatically influence erase characteristics and speed, due to the short control gate channel length, which is a few times of the carrier escape length. A negative voltage application onto the word gate enhances erase speed, whereas a positive channel potential under the word gate reduces erase speed. By effective biasing of the memory array, word line or even single memory cell level erase is possible without area penalty, as compared to erase blocking by triple well or physical block separations of prior art. Near F-N channel erase without substrate bias application and program disturb protection by word line voltage are also included.

Abstract: Provided in the present invention are a high speed and low program voltage nonvolatile memory cell, a programming method for same and a nonvolatile memory array. A nonvolatile memory cell comprises a first gate insulator formed on a surface of a first channel forming semiconductor region adjacent to a source region; a second gate insulator formed on a surface of a second channel forming semiconductor region adjacent to a drain region; a first gate electrode formed on said first gate insulator; and a second gate electrode formed on said second gate insulator wherein the second gate insulator includes a first layer forming a potential barrier at the interface with the second channel forming region; a third layer forming a potential barrier at the interface with the second gate electrode and the second layer between the first and third layers forming a carrier trapping level.

Abstract: Provided in the present invention are a high speed and low program voltage nonvolatile memory cell, a programming method for same and a nonvolatile memory array. A nonvolatile memory cell comprises a first gate insulator formed on a surface of a first channel forming semiconductor region adjacent to a source region; a second gate insulator formed on a surface of a second channel forming semiconductor region adjacent to a drain region; a first gate electrode formed on said first gate insulator; and a second gate electrode formed on said second gate insulator wherein the second gate insulator includes a first layer forming a potential barrier at the interface with the second channel forming region; a third layer forming a potential barrier at the interface with the second gate electrode and the second layer between the first and third layers forming a carrier trapping level.

Abstract: A fast low voltage ballistic program, ultra-short channel, ultra-high density, dual-bit multi-level flash memory is described. The structure and operation of this invention is enabled by a twin MONOS cell structure having an ultra-short control gate channel of less than 40 nm, with ballistic injection which provides high electron injection efficiency and very fast program at low program voltages of 3˜5V. The ballistic MONOS memory cell is arranged in the following array: each memory cell contains two nitride regions for one word gate, and ½ a source diffusion and ½ a bit diffusion. Control gates can be defined separately or shared together over the same diffusion. Diffusions are shared between cells and run in parallel to the side wall control gates, and perpendicular to the word line.

Abstract: An fast program, ultra-high density, dual-bit, multi-level flash memory process, which can be applied to a ballistic step split gate side wall transistor, or to a ballistic planar split gate side wall transistor, which enables program operation by low voltage requirement on the floating gate during program is described. Two side wall floating gates are paired with a single word line select gate, and word lines are arranged to be perpendicular both the bit lines and control gate lines. Two adjacent memory cells on the same word line do not require an isolation region. Also, the isolation region between adjacent memory cells sharing the same bitline is defined by the minimum lithography feature, utilizing a self align fill technique. Adjacent memory cells on the same word line share bitline diffusion as well as a third poly control gate. Control gates allow program and read access to the individual floating gate.

Abstract: An fast program, ultra-high density, dual-bit, multi-level flash memory process, which can be applied to a ballistic step split gate side wall transistor, or to a ballistic planar split gate side wall transistor, which enables program operation by low voltage requirement on the floating gate during program is described. Two side wall floating gates are paired with a single word line select gate, and word lines are arranged to be perpendicular both the bit lines and control gate lines. Two adjacent memory cells on the same word line do not require an isolation region. Also, the isolation region between adjacent memory cells sharing the same bitline is defined by the minimum lithography feature, utilizing a self align fill technique. Adjacent memory cells on the same word line share bitline diffusion as well as a third poly control gate. Control gates allow program and read access to the individual floating gate.

Abstract: In the present invention a nonvolatile memory array architecture can be realized by a fabrication process more compatible to an MOS logic fabrication process as compared with previous nonvolatile memory array architectures. Higher write and/or read speed is possible because of a lower bit line resistance. A high hard bit density near 4F2 is possible when a self-align contact technology and a border less contact technology are used. Connection regions are formed throughout the memory array comprising four cells that are connected to one bit line. The connection regions can be formed in the same processing step with opposite conductivity regions for economy of processing. A plurality of memory cells are two dimensionally disposed in two different directions with connection regions, conductive bit lines extending in the first direction, conductive word lines extending in the second direction, and conductive control lines.