Abstract: A demodulation unit for recovering a transmitted symbol from a received signal that has been modulated using an MDPSK modulation scheme is described. The demodulation unit is configured to, for a current time instant, derive a current sample of a phase signal indicative of a phase of the received signal. Furthermore, the demodulation unit is configured to determine a set of discrimination signals for the current sample of the phase signal, based on the current sample of the phase signal and based on one or more previous samples of the phase signal for one or more previous time instants. In addition, the demodulation unit is configured to determine the transmitted symbol for the current time instant based on the set of discrimination signals.

Abstract: Methods, structures and computer program products for digital sample rate conversion are presented. An input digital sample with a first frequency is converted to an output sample with a second frequency. A sample rate conversion circuit is provided which provides an enhanced transposed farrow structure that enables an optimised trade-off between noise levels and computational complexity. Each output sample is derived by convolution of a continuous time interpolation kernel with a continuous time step function representing the input sample stream. In a sample rate conversion structure, there is a trade-off between the quality and the computational complexity. The quality is defined as a ratio between the (wanted) signal power and the (unwanted) noise power. The computational complexity may be defined as the average number of arithmetic operations that are required to generate one output sample. A higher computational complexity will generally lead to a higher power consumption and larger footprint.

Abstract: The present document discloses circuits and methods for providing an output voltage at an output port. In one of the embodiments, a circuit has a power amplifier having an output. In particular, the circuit may have a first transformer including a first coil and a second coil. Moreover, the circuit may have a first capacitor connected in parallel to the first coil and a second capacitor connected in parallel to the second coil. More particularly, the circuit may be adapted to have a first end of the first coil connected to the output of the power amplifier, and a second end of the first coil connected to the output port of the circuit.

Abstract: An anti-noise signal generator and a method of generating an anti-noise signal are presented. The anti-noise generator includes a first microphone input to receive a first sigma-delta modulated signal at a microphone sampling frequency. The first microphone input is coupled to a combiner via a first path and a second path. The combiner is adapted to combine a first filtered signal from the first path and a second filtered signal from the second path to generate the anti-noise signal. The first path includes a first digital filter adapted to operate at a filter frequency equal or greater than the microphone sampling frequency. The second path includes a second digital filter. The first digital filter may be a sigma-delta based filter that includes a sigma-delta modulator.

Abstract: A single-ended to differential circuit is presented. The circuit may be a single-ended to differential integrator or a single-ended to differential amplifier. The circuit determines a first output and a second output voltage based on an input voltage, first and second reference voltages. The circuit has a first, a second and a third input memory element. The circuit in a first phase, samples a voltage indicative of the input voltage on the first input memory element. The circuit in the first phase, samples a voltage indicative of the first reference voltage on the second input memory element. The circuit in the first phase, samples a voltage indicative of the second reference voltage on the third input memory element. The circuit, in a second phase, determines the first and second output voltage based on the sampled voltages on the first, second, and third input memory elements.

Abstract: A method to fabricate a land grid array wafer level chip scale package is described. A silicon die is provided. A dielectric layer is deposited on the silicon die. An opening is etched through the dielectric layer to a metal pad on the silicon die. At least one redistribution layer is formed over the dielectric layer and contacting the metal pad. At least one copper post is formed on the at least one redistribution layer and forms a land grid array. The wafer is sawed partially through on scribe lines to form cuts exposing sides of the silicon die. Thereafter, a molding compound is applied over the at least one redistribution layer and in the cuts wherein the molding compound encapsulates top and side surfaces of the silicon die.

Abstract: An inverter is presented. The inverter may be configured to receive an input voltage at an input node of the inverter, and to generate an output voltage at an output node of the inverter. The inverter may comprise a first transistor coupled between a supply node and the output node of the inverter. Further, the inverter may comprise a second transistor coupled between the output node of the inverter and a reference node. The input node of the inverter may be coupled to a back-gate of the first transistor and to a back-gate of the second transistor.

Abstract: Methods and devices for distance measuring/ranging, as well as location measurements both in 2D and 3D are presented. More specifically, the methods and devices are for determining the time of arrival of a radio frequency signal. A method of determining a time of arrival of a radio frequency signal in a receiving device as received from a transmitting device includes receiving a radio frequency signal, determining a first phase. The first phase is defined as a phase of the received radio frequency signal. The method also includes obtaining a second phase. The second phase is defined as a phase of a reference radio frequency signal. The method also includes determining the time of arrival of the radio frequency signal based on comparing the first and second phases.

Abstract: A security solution for BLUETOOTH Low Energy (BLE) or equivalent wireless data exchange protocols involves authentication of a peripheral device by a central device using the advertising channel is presented. A method of authenticating a peripheral device in a wireless data exchange has a peripheral device sending an advertising channel Protocol Data Unit (PDU), a central device receiving the advertising channel PDU and the central device sending a scan request scanning PDU to the peripheral device. The advantage of this method of using discovery protocol enables a software based solution for the monitoring device and a hardware with software based solution on the beacon device.

Abstract: An anti-noise signal generator and a method of generating an anti-noise signal are presented. The anti-noise generator includes a first microphone input to receive a first sigma-delta modulated signal at a microphone sampling frequency. The first microphone input is coupled to a combiner via a first path and a second path. The combiner is adapted to combine a first filtered signal from the first path and a second filtered signal from the second path to generate the anti-noise signal. The first path includes a first digital filter adapted to operate at a filter frequency equal or greater than the microphone sampling frequency. The second path includes a second digital filter. The first digital filter may be a sigma-delta based filter that includes a sigma-delta modulator.

Abstract: A sensing device with a phase locked loop circuit that has an oscillator to provide an oscillator output signal is presented. The sensing device has a power amplifier to provide at an output of the power amplifier an amplified output signal based on the oscillator output signal. The amplified output signal has an interfering signal component at the oscillator frequency. The sensing device has a measurement circuit to measure offset information regarding a frequency offset between the oscillator frequency and a target frequency of the oscillator. The frequency offset is due to a frequency pulling effect at the oscillator caused by the interfering signal component of the amplified output signal. The sensing device has a control circuit to use the offset information for trimming the phase locked loop circuit and/or the power amplifier, and/or for determining information regarding an environmental situation at the output of the power amplifier.

Abstract: A frequency divider is provided which uses common circuitry to switch between different duty cycle outputs. The divider has one or more memory elements with a feedback loop and which are controllable to adjust a duty cycle of an output signal. Each memory element has a first regenerative cell and a second regenerative cell, and where one of the regenerative cells is a controllable regenerative cell which can be controlled to vary the duty cycle of an output of the frequency divider circuit. The controllable regenerative cell can be selectively activated so that in a first configuration where the controllable regenerative cell is activated an output of the frequency divider circuit has a first duty cycle and in a second configuration where the controllable regenerative cell is deactivated an output of the frequency divider circuit has a second duty cycle.

Abstract: A signal processing structure and method are presented. A first digital filter operates on received sigma-delta modulated (SDM) input signals. A second pre-processing digital filter receives a SDM input signal, directly low pass filter the SDM input signal and provides an output SDM signal. The output sigma-delta modulated signal is provided as an input for said first digital filter. In standard digital systems operating with digital microphones, filtering of the microphones' output signal requires to first convert the signal into pulse code modulation (PCM), then filter and finally convert back to pulse density modulation (PDM). This approach increases the latency of the system because decimation and interpolation must be performed in order to pass from PDM to PCM. By using filters that operate directly on the oversampled PDM output of the digital microphones it is possible to reduce the latency of the system and minimize the hardware area.

Abstract: This document presents an oscillator circuit and method. The oscillator circuit has a crystal to generate an oscillating voltage signal, a load capacitor coupled to the crystal, a capacitive element, and a switching circuit. The switching circuit alternately connects the capacitive element to the load capacitor and disconnects the capacitive element from the load capacitor. The presented oscillator circuit shows the advantages of a lower power consumption and a smaller circuit area.

Abstract: A method of data calibration, and in particular sensor calibration, which involves gathering an initial first estimate and then binning the data samples, so that calibration can be performed without the need for a known reference stimulus. The present disclosure relates to calibration of vectors in a measurement system, and in particular to calibration of a correction function for systematic errors in successive data vectors. There is provided a method of determining a vector calibration function comprising: binning successive data vectors; and optimising the binned data vectors once data vectors allocated to a minimum number of unique bins have been observed. The method comprises establishing an initial calibration estimate and where the binning and optimising are performed based on said initial calibration estimate.

Abstract: A digital filter and a method for filtering a pulse density modulation (PDM) signal are presented. The digital filter has a first filter circuit to receive an input signal with input values at successive time steps to provide a filtered input signal with filtered values at successive time steps. The digital filter does not require sample-rate or data format conversions. Also, the digital filter is area and power efficient when implemented in hardware. Optionally, the digital filter has a sigma-delta modulator including the quantiser, the sigma-delta modulator being used to receive the filtered input signal and to process the filtered input signal before and/or after being quantised by the quantiser. This digital filter does not require sample-rate or data format conversions. This digital filter is area and power efficient when implemented in hardware.

Abstract: A low power microcontroller that includes a low power node controller adapted to retrieve data from peripheral devices is presented. The microcontroller contains a state machine coupled to a storage medium, which is adapted to store a set of instructions executable by the state machine. The microcontroller also contains a power domain controller, which is adapted to enable the state machine upon receipt of a notification signal. As an option, the microcontroller contains a plurality of communication controllers for communicating with a plurality of external devices, wherein the power domain controller includes a register which may be read by the state machine to identify a communication controller among the plurality controllers. Also, a method of operating a microcontroller for use with an external device is presented. The method provides a state machine which executes a set of instructions.

Abstract: The present document relates to oscillator circuits and a method. An oscillator circuit generates an oscillating voltage signal, wherein the crystal has a first electrode and a second electrode. The oscillator circuit has a power source with a supply terminal and a reference terminal. The oscillator circuit has a switching circuit arranged between the power source and the crystal. The switching circuit, in a start-up phase, alternately connects the supply terminal of the power source to the first and second electrode of the crystal such that an amplitude of the oscillating voltage signal is increased.

Abstract: The present document relates to a Viterbi-based GFSK (Gaussian frequency-shift keying) demodulator that supports different modulation index ranges. In particular, the present document relates to a circuit and a corresponding method for demodulating a base band signal. For example, the base band signal may have an in-phase component and a quadrature component. The method includes determining a phase-modulated signal based on the base band signal. The method includes determining a scaled phase signal by scaling the phase-modulated signal using a scaling factor. The method includes determining discrimination signals based on the scaled phase signal using a periodic discrimination function. The method includes applying a Viterbi algorithm to the discrimination signals for determining an output signal.

Abstract: A computer system, especially but not exclusively an embedded system, is provided with a CPU and an external FLASH or other memory which is used for storing code to be executed by the CPU in operation of the system. The system can be initialized without requiring a secondary boot sequence which means it can be used in preference to embedded or serial FLASH solutions. There is provided a computer system comprising: a processor; an external memory, being external to the processor; a memory controller for the external memory; and a power management unit which is arranged to receive a wake up signal, then to first wake up the memory controller; and secondly at a later time to wake up the processor.