Abstract: Methods, structures and computer program products for digital sample rate conversion are presented. An input digital sample with a first frequency is converted to an output sample with a second frequency. A sample rate conversion circuit is provided which provides an enhanced transposed farrow structure that enables an optimised trade-off between noise levels and computational complexity. Each output sample is derived by convolution of a continuous time interpolation kernel with a continuous time step function representing the input sample stream. In a sample rate conversion structure, there is a trade-off between the quality and the computational complexity. The quality is defined as a ratio between the (wanted) signal power and the (unwanted) noise power. The computational complexity may be defined as the average number of arithmetic operations that are required to generate one output sample. A higher computational complexity will generally lead to a higher power consumption and larger footprint.

Abstract: A method of synchronizing the clocks of a master device and at least a first slave device which are connected on a wireless network. The method includes sending a scan command from the master device to at least the first slave device, setting the master device to a broadcast mode and broadcasting data, the broadcast data comprising a first time stamp; scanning the broadcasting data at at least the first slave device and resetting the clock of the first slave device using the first time stamp. In particular, but not exclusively, the present disclosure relates to synchronizing the clocks of two devices which are connected on a Bluetooth Low Energy (BLE) wireless network.

Abstract: The present document describes a digital power amplifier configured to provide an amplified output signal at an output port based on an input signal. The power amplifier comprises a drive unit configured to generate a high side drive signal comprising a sequence of pulses for controlling the high side switch and a low side drive signal comprising a sequence of pulses for controlling the low side switch, respectively. The drive signals are generated such that the pulses of the high side drive signal are non-overlapping with regards to the pulses of the low side drive signal, and such that the sequence of pulses of the high side drive signal and the sequence of pulses of the low side drive signal have a reduced fraction of energy from higher order harmonics compared to a sequence of rectangular shaped pulses.

Abstract: A power combiner for an outphasing amplifier system comprises an output terminal, a first input terminal, a first inductor, and a first capacitor, wherein the first input terminal is connected to ground via the first inductor and the first input terminal is connected to the output terminal via the first capacitor. The power combiner further comprises a second input terminal, a second capacitor, and a second inductor, wherein the second input terminal is connected to ground via the second capacitor and the second input terminal is connected to the output terminal via the second inductor. The first capacitor can have a same capacitance as the second capacitor and the first inductor has a same inductance as the second inductor.

Abstract: A divider circuit and method for generating one or more digital signals is presented. The circuit has a first output section for generating a first digital signal. There is a first output section with an output node to output the first digital signal, and a plurality of switches with one or more control switches. The plurality of switches selectively couple the output node to a first voltage and/or to selectively couple the output node to a second voltage, thereby generating the first digital signal. The or each control switch is prevents at least one of (i) the output node being coupled to the first and second voltages simultaneously and (ii) the output node being decoupled from both the first and second voltages simultaneously.

Abstract: A digital active diode circuit for letting current pass in one direction and substantially blocking current in the opposite direction is presented. The circuit contains switching means comprising an array of switches, a first comparison unit coupled to the digital active diode circuit input and output. The first comparison unit updates its output if the difference between their inputs is higher than a first threshold voltage, and a second comparison unit being coupled to the digital active diode circuit output and input. The second comparison unit updates its output if the difference between its inputs is lower than a second threshold voltage. The switching means switches on or off at least one switch based on the comparisons performed by the first comparison unit and the second comparison unit and wherein the first threshold voltage is different from the second threshold voltage.

Abstract: A circuit for controlling a power supply is disclosed. The circuit has a storage element for storing energy harvested from energy sources, a backup battery, and a comparator to compare a voltage of the storage element to a reference voltage. The circuit also contains a first switch for selectively connecting the storage element to an output. A second switch connects the backup battery to the output. A switch control circuit controls the first switch to disconnect the storage element from the output and the second switch to connect the backup battery to the output, if the voltage of the storage element is below the reference voltage. The backup battery is disconnected from the output while the voltage of the storage element is below the reference voltage. The control circuit controls the second switch to disconnect the battery from the output while the voltage of the storage element is below the reference.

Abstract: An auto-calibrated current sensing comparator is provided. A secondary dynamic comparator shares the same inputs and acts to adjust a calibration control of the current sensing comparator. The calibration control may be in the form of adjusting the offset of the current sensing comparator or adjusting a propagation delay that is added to its output.

Abstract: An impedance detector for measuring an impedance of a circuit comprises a frequency source, a resistor connected in between the frequency source and the circuit to be measured, a phase shift circuit for applying a phase shift to a signal from the frequency source, a first multiplier for mixing the signal from the frequency source with a signal from the circuit to be measured, a second multiplier for mixing the phase shifted signal with the signal from the circuit to be measured, and a processing circuit for determining an indication of an impedance of the circuit to be measured in dependence on the first mixed signal and the second mixed signal.

Abstract: A charge pump circuit suitable for low input voltages is presented. The charge pump circuit has a first clock signal generator, a second clock signal generator, and n voltage doubler circuits. The voltage doubler has an input, an output, a first capacitor connected to the first clock signal generator, a second capacitor connected to the second clock signal generator, a first NMOST having the source connected to the input and the drain connected to the first capacitor, a second NMOST having the connected to the source of the first NMOST and the drain connected to second capacitor, a first PMOST having the drain connected to the first capacitor and the source connected to the output, a second PMOST having the source connected to the source of the first PMOST and the drain connected to the second capacitor.

Abstract: The present disclosure relates to methods and circuits to lowering the signal range of switching or logic circuits below supply range. The circuits may have one or more stages. The supply levels can be set individually for each stage. This may realize amplifiers/attenuators, both digitally and analogically controlled, based on progression and/or modulation in the supply range from stage to stage. A chain of stages can provide the desired power gain by setting the supply progression according to the nature of the incoming signals. The signal levels are lowered by generic device networks comprising voltage sources providing voltages independent of currents flowing through. Decoupling the signal amplitude from DC biasing allows for the signal swing to be lower than threshold voltages of the active devices.

Abstract: A patching system and a patching circuit provide a type of patching entry which can replace several sequential memory positions with hardcoded and dynamically configured assembly instructions, thus injecting a small piece of code. The operation of the injected code can be for any purpose, but as an example may be used to seamlessly redirect the execution flow of a processing unit.

Abstract: An optimised method for driving a loudspeaker is used for protecting the loudspeaker from damage due to excessive excursion or from overheating. The playback power of an incoming audio data stream is compared with a feedback power derived from the loudspeaker actuator and the comparison is used to adjust the frequency response of the loudspeaker, across individual sub bands.

Abstract: An on-chip thermoelectric generator comprises an integrated circuit comprising a substrate and at least one thermocouple integrated with the substrate, wherein the thermocouple is configured to convert a temperature difference into a voltage. A metal bump or metal pillar is thermally connected to a portion of the thermocouple for generating the temperature difference. The metal bump or metal pillar is electrically insulated from said at least one thermocouple. The metal bump or metal pillar is electrically connected to a component of the integrated circuit which is different from the thermocouple.

Abstract: An oscillator circuit with an oscillator stage and a first current source arranged to drive the oscillator stage is presented. The oscillator stage has an oscillator stage input terminal, an oscillator stage output terminal, an oscillator arranged to provide an oscillating signal between the oscillator stage input terminal and the oscillator stage output terminal. The oscillator circuit has an operational amplifier with an inverting input, a non-inverting input and an operational amplifier output. The oscillator stage input terminal and the oscillator stage output terminal are coupled to the inverting input and non-inverting input. The operational amplifier output is coupled to the oscillator stage input terminal such that the oscillator stage input terminal and the oscillator stage output terminal are controlled to have a same DC voltage level.

Abstract: A device for true random number generation is disclosed. The device comprises an antenna and an analog processing unit for analog processing of a signal received from the antenna. An analog to digital (AD) converter is used for converting an analog signal generated by the analog processing unit into a digital signal. An isolation means is applied for temporarily isolating the antenna from the analog processing unit and the AD converter to generate a noise signal. A sampling means is used for sampling output values generated by the AD converter when the antenna is isolated from the analog processing unit and the AD converter. A digital processing unit is used for processing the sampled output values generated by the AD converter. The digital processing unit is configured to generate a random number based on one or more of the output values generated by the AD converter.

Abstract: An infrared signal generator with an interface for receiving an encoded infrared command; and protocol generation circuitry for generating a bitstream that comprises one or more data words that comprise data to be transmitted and one or more protocol words that describe symbols of an infrared protocol is presented. Optionally, the protocol generation circuitry comprises a first circuit for generating a data word and a second circuit for generating a protocol word. Optionally, the infrared signal generator comprises a carrier frequency generator which is selectively combined with the output of either the first circuit or the second circuit to provide a drive signal for an infrared transmitter.

Abstract: An electronic circuit is disclosed for dividing the frequency of a periodic signal, wherein at least one of the memory elements is arranged with its output terminal connected to the input terminal of another memory element wherein the electronic circuit is configured to generate an output signal having a smaller fundamental frequency than the clock signal at at least one of the output terminals. Each memory element is configured to change and hold a voltage at the output terminal based on a voltage at the input terminal at times controlled by a clock signal received at the clock terminal. At least two of the memory elements are stacked in the sense that the bottom terminal of a first memory element is connected to the top terminal of a second memory element to enable the charge to flow from the first memory element to the second memory element.

Abstract: An automatic calibration of a clock of a wireless portable part with respect to a clock of a fixed part in a field environment. The calibration performed in the field environment negates the need to calibrate the clock during manufacture and negates the need for an initial field recalibration because of temperature differences between manufacture and the field. In performing the calibration the frequency of the clock of the portable part is varied until the portable part is synchronous with the fixed part to with in a range of timing bits. The portable part is declared calibrated after remaining calibrated for a defined number of data frames.

Abstract: A method and apparatus for executing an application program stored in an one-time-programmable, OTP, memory in a system on chip (SoC) is described. The SoC has RAM, a CPU and an OTP controller. The OTP memory stores an application program. The method includes, by the processor unit at power-up, instructing the OTP controller to copy the application program from the OTP memory to RAM, executing the application program from RAM, and setting the system on chip (SoC) in sleep mode. By the OTP controller after a wake-up, copying the application program from the OTP memory to the RAM and after the copying, waking up the CPU and transferring control back to the CPU. By the CPU after being woken up by the OTP controller, executing the application program from RAM.