Patents Assigned to Dialog Semiconductor (UK) Limited
  • Patent number: 10469065
    Abstract: A circuit for operating a transistor device that acts as a switch is presented. The circuit includes the transistor device and a control circuit coupled to a gate of the transistor device. The control circuit is adapted to selectively apply at least a first voltage level, a second voltage level, and a third voltage level to the gate of the transistor device, wherein the first, second, and third voltage levels are distinct voltage levels. The disclosure further relates to a method of operating a transistor device that acts as a switch. The proposed circuit provides additional gate voltages, by contrast to conventional two-level gate drivers. By appropriate choice of the additional gate voltages, reverse mode conductance losses of the transistor device can be reduced and/or to the Safe Operating Area (SOA) of the transistor device can be improved.
    Type: Grant
    Filed: March 1, 2018
    Date of Patent: November 5, 2019
    Assignee: Dialog Semiconductor (UK) Limited
    Inventors: Horst Knoedgen, Christoph N. Nagl, Nebojsa Jelaca, Frank Kronmueller, Ambreesh Bhattad
  • Patent number: 10468984
    Abstract: An object of this disclosure is to implement a Buck, Boost, or other switching converter, with a circuit to supply a reference voltage and Adaptive Voltage Positioning (AVP), by a servo and programmable load regulation. The reference voltage is modified, achieving a high DC gain, using a servo to remove any DC offset at the output of the switching converter. The correction implemented by the servo is measured, and a programmable fraction of the correction is injected back on either the reference voltage or the output feedback voltage. To accomplish at least one of these objects, a Buck, Boost, or other switching converter is implemented, consisting of an output stage driven by switching logic, with a servo configured between the reference voltage and the control loops of the Buck converter. The AVP function is implemented on either the reference voltage or output feedback voltage.
    Type: Grant
    Filed: July 1, 2016
    Date of Patent: November 5, 2019
    Assignee: Dialog Semiconductor (UK) Limited
    Inventors: Pietro Gallina, Vincenzo Bisogno, Mark Childs
  • Patent number: 10459470
    Abstract: A digital voltage regulator and a method to regulate an output voltage at an output node based on an input voltage is presented. The regulator has a driver stage with N driver slices, with N>1. Each of the N driver slices can be activated or deactivated individually. A driver slice comprises a current source to provide an output current component to the output node, if the driver slice is activated. Furthermore, the regulator has a control unit to activate a number n of the N driver slices, based on a deviation of a feedback voltage from a reference voltage, where the feedback voltage is dependent on the output voltage.
    Type: Grant
    Filed: May 11, 2018
    Date of Patent: October 29, 2019
    Assignee: Dialog Semiconductor (UK) Limited
    Inventors: Mihail Jefremow, Dan Ciomaga, Gennadii Tatarchenkov, Stephan Drebinger, Fabio Rigoni, Alessandro Angeli, Petrus Hendrikus Seesink
  • Patent number: 10461639
    Abstract: Current in a switching converter is controlled using a current-mode hysteretic controller. The high-side switch (usually a PMOS) is turned off when the current in the coil exceeds a certain peak control current. The low-side switch (usually an NMOS) is turned off when the current in the coil falls below a certain valley control current. A current ramp is added to one of these control currents, either peak or valley. The current ramp is initiated by a reference clock signal, which has the effect of synchronizing the switching converter to the reference clock.
    Type: Grant
    Filed: August 23, 2018
    Date of Patent: October 29, 2019
    Assignee: Dialog Semiconductor (UK) Limited
    Inventor: Mark Childs
  • Patent number: 10461555
    Abstract: A wired connection, such as USB-C, for charging a sink from a source, has a configuration channel and a power transmission channel. The presence of data on the configuration channel is used to determine that a cable has been disconnected from the power source. This charging system contains a capacitive power converter and a controller for controlling the capacitive power converter. There is also a configuration channel detector, which is arranged to detect the status of the configuration channel and to provide this status to the controller, so that the system can determine that the source has been detached from the bus when no configuration channel data is present.
    Type: Grant
    Filed: May 18, 2017
    Date of Patent: October 29, 2019
    Assignee: Dialog Semiconductor (UK) Limited
    Inventors: Sabin Eftimie, Lasse Harju, Manfred Kogler, Amit Bavisi, Sorin Negru
  • Patent number: 10454291
    Abstract: A power supply has a multi-level DC-DC converter and a battery pack with two or more cells provided in series. The switching DC-DC converter provides a regulated voltage at an output. The converter has an energy storage element. The switching regulator is designed to selectively operate in two or more different modes. It switches between a first mode where one cell is connected (between battery and inductor of the converter), and the converter functions like a single cell buck converter and a second mode where two cells are connected in series and the converter functions like a two series cell buck converter. In general, any number of cells and modes can be provided, with successive cells being connected in series in each mode.
    Type: Grant
    Filed: April 12, 2017
    Date of Patent: October 22, 2019
    Assignee: Dialog Semiconductor (UK) Limited
    Inventor: Holger Petersen
  • Patent number: 10447288
    Abstract: This disclosure relates to an analog-to-digital converter, ADC.
    Type: Grant
    Filed: December 20, 2018
    Date of Patent: October 15, 2019
    Assignee: Dialog Semiconductor (UK) Limited
    Inventor: Ivan Muhoberac
  • Patent number: 10439421
    Abstract: A linear charger circuit and method for providing an output current at an output node is presented. The circuit contains a pass device connected between an input node and the output node, first and second replica devices connected in parallel to the pass device, with their control terminals coupled to a control terminal of the pass device. The first replica device is coupled to a first circuit path for determining whether current output by the linear charger circuit shall be terminated. The second replica device is coupled to a second circuit path for providing feedback for controlling the pass device, a control circuit coupled to the second circuit path for controlling the pass device based on a quantity indicative of a current flowing through the second circuit path, and a switching circuit coupled to the second circuit path.
    Type: Grant
    Filed: July 31, 2017
    Date of Patent: October 8, 2019
    Assignee: Dialog Semiconductor (UK) Limited
    Inventors: Mihail Jefremow, Selcuk Talay, Fabio Rigoni
  • Patent number: 10439528
    Abstract: An actuation system is proposed for an optical system, comprising a voice coil motor for actuating the optical system, the voice coil motor comprising a magnet and an electric coil, a position measuring unit for measuring the position of the electric coil and providing a position feedback signal, and a control unit for closed loop control of the position of the optical system based on a target position and the position feedback signal, used for generating a drive signal for the electric coil. According to the disclosure, a ferromagnetic element is arranged in proximity to the electric coil so that the inductance of the electric coil depends on its position. Further, the position-measuring unit measures the inductance of the electric coil and determines the position of the electric coil based on the determined inductance.
    Type: Grant
    Filed: August 17, 2018
    Date of Patent: October 8, 2019
    Assignee: Dialog Semiconductor (UK) Limited
    Inventors: Horst Knoedgen, Horst Schleifer
  • Patent number: 10432155
    Abstract: A bias current generator is disclosed that include an operational amplifier that is self-biased during an inactive period with a bias current to bias a gate of an output transistor. Since the inactive period bias is close to an active period bias applied to the gate of the output transistor during active operation of the bias current generator, the speed of transition from the inactive period to the active period is enhanced by the self-biasing of the operational amplifier.
    Type: Grant
    Filed: February 7, 2018
    Date of Patent: October 1, 2019
    Assignee: DIALOG SEMICONDUCTOR (UK) LIMITED
    Inventor: Pranav Kotamraju
  • Patent number: 10432088
    Abstract: A two-stage power converter is disclosed in which a second stage may command a first stage to adjust an output voltage from the first stage to compensate for PVT variations in the second stage. Alternatively, the second stage may adjust a clocking frequency to compensate for the PVT variations.
    Type: Grant
    Filed: June 5, 2018
    Date of Patent: October 1, 2019
    Assignee: DIALOG SEMICONDUCTOR (UK) LIMITED
    Inventor: Kevin Yi Cheng Chang
  • Patent number: 10425075
    Abstract: Driver circuits with S-shaped gate drive voltage curves for ramp-up and ramp-down of power field effect transistors are presented. In ramp-up, the S-shaped curve rapidly ramps the gate voltage of the power FET to its threshold. This ramp-up is self-terminating. The gate voltage of the power FET is slewed through saturation with a time constant. After a predetermined time, the gate of the power FET is driven to approach the supply voltage level. In ramp-down, the S-shaped curve rapidly ramps the gate voltage of the power FET down to its threshold voltage. This ramp-down is self-terminating. The gate voltage of the power FET is slewed through saturation. The gate-source voltage of the power FET is rapidly ramped down to zero. Such S-shaped curves for the gate drive signal allow the control of the transition times of the gate drive signal to acceptable levels of voltage/current spikes and electromagnetic interference.
    Type: Grant
    Filed: April 30, 2018
    Date of Patent: September 24, 2019
    Assignee: Dialog Semiconductor (UK) Limited
    Inventors: Kelly Consoer, Bryan Quinones, Kevin Yi Cheng Chang, Mark Mercer
  • Patent number: 10418909
    Abstract: A DC-DC switching converter is described, with a high magnetic coupling ratio between coils connected directly to a supply and ground, and with pass-device switches connected directly to an output. The pass-device switches are driven in such a way that the coils are magnetized alternately. The DC-DC switching converter may use multiple output switches, to supply multiple outputs. The DC-DC switching converter may use different turns-ratio on the coils, to adjust the duty-cycle of the switching converter operates, for a given supply voltage to output voltage ratio.
    Type: Grant
    Filed: July 24, 2018
    Date of Patent: September 17, 2019
    Assignee: Dialog Semiconductor (UK) Limited
    Inventor: Mark Childs
  • Patent number: 10418342
    Abstract: A method to fabricate a reconstructed panel based fan-out wafer level package is described. A reconstructed wafer panel is provided comprising a plurality of individual dies encapsulated in a first molding compound. Interconnected metal redistribution layers (RDL) separated by PSV layers are formed on top surfaces of the plurality of individual dies. Thereafter, the reconstructed wafer panel is cut into a plurality of rectangular strips. Thereafter, backend processing is performed on each of the plurality of rectangular strips.
    Type: Grant
    Filed: April 26, 2018
    Date of Patent: September 17, 2019
    Assignee: Dialog Semiconductor (UK) Limited
    Inventor: Ian Kent
  • Patent number: 10410996
    Abstract: An integrated circuit IC package with one or more pins protruding from the IC package for electrically connecting the IC package with a printed circuit board PCB is presented. The IC package has a first die with a first electronic component, a second die with a second electronic component, and a conductive plate having a plane surface. The first electronic component may be a semiconductor power device and the second electronic component may be a control circuit. The plane surface of the conductive plate is electrically connected to both a plane surface of the first die and one or more pins such that an electrical connection is established between the first die and the one or more pins. The second die may be arranged on top of the conductive plate. Alternatively, a third die with a third electronic component may be arranged on top of the conductive plate.
    Type: Grant
    Filed: December 2, 2016
    Date of Patent: September 10, 2019
    Assignee: Dialog Semiconductor (UK) Limited
    Inventors: Melvin Martin, Baltazar Canete, Jr., Macario Campos, Rajesh Aiyandra
  • Patent number: 10404173
    Abstract: A buck-boost switching converter which receives an input voltage and provides an output voltage is presented. The converter contains a first set of switches having a first power switch and a first ground switch, a second set of switches having a second power switch and a second ground switch. A controller is arranged to send control signals to the first and second set of switches. The controller is arranged such that in a buck mode, the first set of switches operates to provide buck regulation while the second power switch is held in a closed state. In a boost mode, the second set of switches operates to provide boost regulation while the first power switch is held in a closed state, and the controller is arranged to selectively operate the buck-boost switching converter in the buck mode or the boost mode based on a length of a time period.
    Type: Grant
    Filed: March 20, 2018
    Date of Patent: September 3, 2019
    Assignee: Dialog Semiconductor (UK) Limited
    Inventor: Guillaume de Cremoux
  • Patent number: 10396004
    Abstract: A wafer level chip scale package is described. The wafer level chip scale package comprises a plurality of redistribution layer (RDL) traces connected to a silicon wafer through openings through a first polymer layer to metal pads on a top surface of the silicon wafer. A plurality of underbump metal (UBM) layers each contact one of the plurality of RDL traces through openings in a second polymer layer over the first polymer layer. A plurality of solder bumps lie on each UBM layer. A metal plating layer lies under the first polymer layer and does not contact any of the plurality of RDL traces. At least one separator lies between at least two of the plurality of RDL traces. The separator is a metal fencing between the two neighboring RDL traces or an air gap between the two neighboring RDL traces.
    Type: Grant
    Filed: January 25, 2018
    Date of Patent: August 27, 2019
    Assignee: Dialog Semiconductor (UK) Limited
    Inventors: Habeeb Mohiuddin Mohammed, Rajesh Subraya Aiyandra
  • Patent number: 10382050
    Abstract: An analog-to-digital converter ADC and a method to convert an analog input signal into a digital output signal comprising N bits on, n?{0, . . . , N?1} is presented. The ADC contains a controller, a digital-to-analog converter DAC, and a comparator. The comparator generates a binary signal by comparing the analog input signal with an analog output signal of the DAC. The controller receives the binary signal generated by the comparator and generates, based on the binary signal, a digital control signal comprising N bits cn, n?{0, . . . , N?1}. The DAC generates the analog output signal based on the digital control signal generated by the controller. The controller has a register which stores a previous sum value and an adder to determine a test sum value by adding.
    Type: Grant
    Filed: May 25, 2018
    Date of Patent: August 13, 2019
    Assignee: Dialog Semiconductor (UK) Limited
    Inventors: Donesh Gillin, Arun Sundar, Bindhu Vasu
  • Patent number: 10381828
    Abstract: An overvoltage protection circuit for a transistor device is presented. The overvoltage protection circuit comprises a first pin coupled to a gate terminal of the transistor device, an electrostatic discharge protection circuit coupled between a second pin and a source terminal of the transistor device, a first diode coupled between the first pin and the second pin, and a second diode coupled in parallel to the first diode between the first pin and the second pin. The forward direction of the first diode is opposite to the forward direction of the second diode. In addition, A method of measuring a gate leakage current of a transistor device and a method of bonding a transistor device coupled to such an overvoltage protection circuit are presented.
    Type: Grant
    Filed: January 29, 2018
    Date of Patent: August 13, 2019
    Assignee: Dialog Semiconductor (UK) Limited
    Inventors: Horst Knoedgen, Christoph N. Nagl, Nebojsa Jelaca
  • Patent number: 10381927
    Abstract: The disclosure describes a DC-DC switching converter providing a peak-current servo, employing a pulse-frequency modulation (PFM) control signal and a constant on-time. A Buck, Boost, Buck-Boost, or similar switching converter that supports PFM mode is required, using a fixed on-time scheme for PFM. A final value of the coil current is sampled, and the sampled value of the coil current is compared to a target value for the coil current, to establish whether it is greater or less than the target value. The on-time of the high side device is adjusted to bring the final value of the coil current closer to the target value, using an adaptive coil current measurement.
    Type: Grant
    Filed: July 17, 2017
    Date of Patent: August 13, 2019
    Assignee: Dialog Semiconductor (UK) Limited
    Inventor: Mark Childs