Patents Assigned to Dialogic (US) Inc.
  • Patent number: 10848056
    Abstract: A system for improving a power factor (PF) of a power converter in signal communication with a rectifier and an electromagnetic interference capacitor is disclosed. The system includes a controller and a threshold detector. The threshold detector is configured to measure and compare a rectified voltage against a threshold voltage and the controller is configured to set the power converter to a stop-mode. The power converter is set to the stop-mode at a stop-time that is less than a first zero-crossing time. The controller is further configured to set the power converter to a run-mode at a time that is past the first zero-crossing time.
    Type: Grant
    Filed: August 19, 2019
    Date of Patent: November 24, 2020
    Assignee: DIALOG SEMICONDUCTOR INC.
    Inventors: Naidong Xu, Laiqing Ping, Nan Shi
  • Patent number: 10848174
    Abstract: A digital filter and a method for filtering a pulse density modulation (PDM) signal are presented. The digital filter has a first filter circuit to receive an input signal with input values at successive time steps to provide a filtered input signal with filtered values at successive time steps. The digital filter does not require sample-rate or data format conversions. Also, the digital filter is area and power efficient when implemented in hardware. Optionally, the digital filter has a sigma-delta modulator including the quantiser, the sigma-delta modulator being used to receive the filtered input signal and to process the filtered input signal before and/or after being quantised by the quantiser. This digital filter does not require sample-rate or data format conversions. This digital filter is area and power efficient when implemented in hardware.
    Type: Grant
    Filed: May 9, 2019
    Date of Patent: November 24, 2020
    Assignee: Dialog Semiconductor B.V.
    Inventors: Ashley Hughes, Wessel Harm Lubberhuizen
  • Patent number: 10840806
    Abstract: The clock input of a buck converter is delayed, and the delay is controlled proportionally to the preceding high-side output switch on time. In the steady state, the high-side switch on time is uniform, and the clock is offset by a fixed amount. When sub-harmonic oscillation begins to occur, the high-side switch on time may increase during a cycle. The longer high-side on time causes the clock to be delayed by an increased amount. This has the effect of increasing the following low-side output switch on time. This further increases the subsequent high-side on time, and counteracts the effects of sub-harmonic oscillation. If the system is properly controlled, loop compensation is implemented correctly and sub-harmonic oscillation is prevented. In addition, the scheme may also be configured for the delay to be controlled proportionally to the preceding low-side output switch on time of the buck converter.
    Type: Grant
    Filed: May 25, 2017
    Date of Patent: November 17, 2020
    Assignee: Dialog Semiconductor (UK) Limited
    Inventors: Mark Childs, Jens Masuch
  • Patent number: 10840894
    Abstract: The present document discloses a circuitry for delaying a digital input signal. In particular, the circuitry may comprise a delay cell circuit and a reciprocal current digital-to-analog converter (DAC). The delay cell circuit may be coupled to the reciprocal current DAC. More particularly, the reciprocal current DAC may be configured to output a charge current to the delay cell circuit according to a value of a control input provided to the reciprocal current DAC. The charge current output by the reciprocal current DAC may be inversely proportional to the value of the control input, wherein the delay depends on the charge current.
    Type: Grant
    Filed: August 8, 2019
    Date of Patent: November 17, 2020
    Assignee: Dialog Semiconductor (UK) Limited
    Inventors: Gary Hague, Rupert Howes, Ambreesh Bhattad
  • Patent number: 10840798
    Abstract: A high-voltage power converter with a high-side switch coupled with a high-voltage input and a high-side switch control coupled with the high-side switch are presented. The high-side switch control drives the high-side switch on and off. There is a low-side switch coupled via an output node to the high-side switch. The low-side switch is on when the high-side switch is off and vice versa. A supply capacitor is coupled with a low-voltage supply terminal. The high-side switch control to provides a supply voltage for the high-side switch control. A communication module is coupled with the high-side switch control to provide a bidirectional communication between the high-side switch control and a control system that operates in a low-voltage domain, wherein the communication to and from the high-side switch control is enabled when the low-side switch is on and the high-side switch is off.
    Type: Grant
    Filed: September 28, 2018
    Date of Patent: November 17, 2020
    Assignee: Dialog Semiconductor (UK) Limited
    Inventors: Nebojsa Jelaca, Horst Knoedgen, Christoph N. Nagl
  • Patent number: 10840914
    Abstract: A frequency divider unit to receive an oscillating signal and to update, at an output of the frequency divider unit, a frequency-divided oscillating signal is presented. The frequency divider unit has a first clocked signal inverter to update, clocked based on the oscillating signal, a first intermediate signal at an output of the first clocked signal inverter. The frequency divider unit has a second clocked signal inverter, wherein the output of the first clocked signal inverter may be connected to an input of the second clocked signal inverter, and wherein the second clocked signal inverter updates, clocked based on the oscillating signal, a second intermediate signal at an output of the second clocked signal inverter. The frequency divider unit has a continuously operating signal inverter coupled between the output of the second clocked signal inverter and the input of the first clocked signal inverter.
    Type: Grant
    Filed: September 3, 2019
    Date of Patent: November 17, 2020
    Assignee: Dialog Semiconductor B.V.
    Inventors: Armin Tavakol, Johannes Gerardus Willms
  • Patent number: 10833666
    Abstract: A voltage proportional to a pulse width modulation (PWM) duty cycle is generated, using a low pass filter (LPF). A 2nd or higher order LPF is provided, giving a 90×(2n+1) degree phase shift for (n=0, 1, 2, . . . ), so that the sampling timing at the latter stages can be at the rising and/or falling edge of the PWM input signal. A switched capacitor circuit after the 2nd or higher order LPF is provided, removing a voltage ripple on an LPF output, and using a smaller device area.
    Type: Grant
    Filed: September 17, 2019
    Date of Patent: November 10, 2020
    Assignee: Dialog Semiconductor (UK) Limited
    Inventors: Keisuke Kadowaki, Naoyuki Unno, Hiromitsu Aoyama
  • Patent number: 10833687
    Abstract: A method and associated system have been proposed to achieve power savings in PWM DACs by truncating PWM sequences and maximizing the amount of time available to power up a DAC cell without sacrificing sensitivity to element mismatch. The DAC circuit includes a driver to receive a digital input and to provide a plurality of drive sequences, a digital-to-analog converter, and a controller. The digital-to-analog converter includes an array of digital-to-analog elements operable over several time steps. Upon identifying that the digital signal is below a threshold value, the controller is configured to shorten the drive sequences; and for each time step to identify a first set of elements and a second set of elements among the array of digital-to-analog elements; to apply the shortened drive sequences to the first set; to disable the second set; and to shift the first set and the second set by one element.
    Type: Grant
    Filed: June 17, 2019
    Date of Patent: November 10, 2020
    Assignee: Dialog Semiconductor (UK) Limited
    Inventor: Joseph Hamilton
  • Patent number: 10811970
    Abstract: An object of this disclosure is to implement a Buck, Boost, or other switching converter, with a circuit to supply a reference voltage and Adaptive Voltage Positioning (AVP), by means of a servo and programmable load regulation. The reference voltage is modified, achieving a high DC gain, using a servo to remove any DC offset at the output of the switching converter. The correction implemented by the servo is measured, and a programmable fraction of the correction is injected back on either the reference voltage or the output feedback voltage. To accomplish at least one of these objects, a Buck, Boost, or other switching converter is implemented, consisting of an output stage driven by switching logic, with a servo configured between the reference voltage and the control loops of the Buck converter. The AVP function is implemented on either the reference voltage or output feedback voltage.
    Type: Grant
    Filed: October 21, 2019
    Date of Patent: October 20, 2020
    Assignee: Dialog Semiconductor (UK) Limited
    Inventors: Pietro Gallina, Vincenzo Bisogno, Mark Childs
  • Patent number: 10811974
    Abstract: A hybrid power converter and a method with low power losses over an extended conversion range are presented. The converter maintains low conversion losses associated with reduced inductor ripples not only for a single conversion ratio, but over a wide range of conversion ratios. The power converter has a ground terminal, an input terminal for receiving an input voltage and an output terminal for providing an output voltage with a target conversion ratio. The power converter has an inductor; a first flying capacitor selectively coupled to the inductor; a second flying capacitor selectively coupled to the inductor; a network of switches; and a driver adapted to operate the converter in a first mode associated with a first range of conversion ratios.
    Type: Grant
    Filed: April 17, 2019
    Date of Patent: October 20, 2020
    Assignee: Dialog Semiconductor (UK) Limited
    Inventor: Holger Petersen
  • Patent number: 10811978
    Abstract: An adaptive pulse width modulation threshold is provided for a flyback converter that controls the transition between the pulse frequency mode of operation and the pulse width modulation mode of operation. The adaptive pulse width modulation mode is adapted responsive to an output voltage for the flyback converter.
    Type: Grant
    Filed: June 24, 2019
    Date of Patent: October 20, 2020
    Assignee: DIALOG SEMICONDUCTOR INC.
    Inventors: Cong Zheng, Jing Guo, Chien-Liang Chen
  • Patent number: 10806345
    Abstract: An apparatus for monitoring a physiological parameter over a plurality of measurement periods is presented. The apparatus includes a circuit coupled to a light emitter and to a light receiver. The circuit is adapted to drive the light emitter with a constant first charge over the plurality of measurement periods. Also presented is a wearable device provided with an apparatus for monitoring a physiological parameter over a plurality of measurement periods. Also presented is a method for monitoring a physiological parameter over a plurality of measurement periods, the steps include providing a light emitter and a light receiver and driving the light emitter with a constant first charge over the plurality of measurement periods.
    Type: Grant
    Filed: June 13, 2017
    Date of Patent: October 20, 2020
    Assignee: Dialog Semiconductor B.V.
    Inventor: Marinus Wilhelmus Kruiskamp
  • Patent number: 10804794
    Abstract: A charge pump controller for controlling a charge pump adapted to convert an input voltage into an output voltage with a conversion ratio is presented. The charge pump is operable in a plurality of modes corresponding to different conversion ratios. The controller includes a first selector for selecting a mode of operation of the charge pump. The first selector comprises a first input for coupling to a voltage supply; and a second input for coupling to a source signal. The first selector identifies a target value of the output voltage. The selector calculates a product of the conversion ratio and the input voltage. The selector compares the product with the target value and selects a mode of operation of the charge pump by increasing or decreasing the conversion ratio based on the comparison. The selector maintains the conversion ratio for a length of time before decreasing the conversion ratio.
    Type: Grant
    Filed: September 19, 2018
    Date of Patent: October 13, 2020
    Assignee: Dialog Semiconductor (UK) Limited
    Inventor: Guillaume de Cremoux
  • Patent number: 10804795
    Abstract: The proposed Power Management Integrated Circuit (PMIC) features the option to synchronize the charge-pump of a PMIC with the system clock, and then to swap and self-oscillate and skip pulses, when the digital controls of the PMIC send a first order to the charge-pump. The clock control circuitry of the PMIC also features the option for the charge-pump to then swap and use the system clock again, when the digital controls of the PMIC send a second order to the charge-pump. The designed transition of the clock from clock sync-mode to self-oscillate, and from self-oscillate back to clock sync-mode, does not present any phase discontinuity.
    Type: Grant
    Filed: December 20, 2018
    Date of Patent: October 13, 2020
    Assignee: Dialog Semiconductor (UK) Limited
    Inventor: Guillaume de Cremoux
  • Patent number: 10804802
    Abstract: A power converter comprises a high side switching element and a low side switching element arranged in series between an input terminal of the power converter and a reference terminal. A first feedback circuit of the power converter is configured to control an output voltage or an output current at an output terminal of the power converter. The first feedback circuit comprises a first comparator configured to generate a first control signal for controlling the switching of the switching elements by comparing a first error voltage with a first ramp signal. A second feedback circuit of the power converter is also configured to control said output voltage or said output current. The second feedback circuit comprises a second comparator configured to generate a second control signal by comparing a second error voltage with a second ramp signal.
    Type: Grant
    Filed: October 18, 2018
    Date of Patent: October 13, 2020
    Assignee: Dialog Semiconductor (UK) Limited
    Inventor: Francesco Dalena
  • Patent number: 10797610
    Abstract: A synchronous rectifier controller method is provided for controlling the on and off periods of a synchronous rectifier (SR) switch transistor in a switching power converter. The method includes a first step of monitoring an unfiltered to control whether the SR switch transistor is turned on during a first part of a power switch cycle. The method also includes a second step of monitoring a filtered SR switch signal to control whether the SR switch is turned on during a remaining second part of the power switch cycle.
    Type: Grant
    Filed: September 3, 2019
    Date of Patent: October 6, 2020
    Assignee: DIALOG SEMICONDUCTOR INC.
    Inventors: Pengju Kong, Tao Li, Hien Bui, Wenbo Liang, Hanguang Zhang
  • Patent number: 10797608
    Abstract: A flyback converter communication channel is provided that comprises a pair of capacitors. A transmitter on a first side of a transformer for the flyback converter transmits a transmitter signal over a first one of the capacitors. The transmitter also transmits a complement of the transmitter signal over a second one of the capacitors. A receiver on a second side of the transformer controls a switch transistor responsive to a high-pass-filtered difference of the received signals from the pair of capacitors.
    Type: Grant
    Filed: February 14, 2019
    Date of Patent: October 6, 2020
    Assignee: DIALOG SEMICONDUCTOR INC.
    Inventors: Wenduo Liu, Kun Yang, Laiqing Ping
  • Patent number: 10797012
    Abstract: A multi-pin wafer level chip scale package is achieved. One or more solder pillars and one or more solder blocks are formed on a silicon wafer wherein the one or more solder pillars and the one or more solder blocks all have a top surface in a same horizontal plane. A pillar metal layer underlies the one or more solder pillars and electrically contacts the one or more solder pillars with the silicon wafer through an opening in a polymer layer over a passivation layer. A block metal layer underlies the one or more solder blocks and electrically contacts the one or more solder pillars with the silicon wafer through a plurality of via openings through the polymer layer over the passivation layer wherein the block metal layer is thicker than the pillar metal layer.
    Type: Grant
    Filed: August 25, 2017
    Date of Patent: October 6, 2020
    Assignee: Dialog Semiconductor (UK) Limited
    Inventors: Habeeb Mohiuddin Mohammed, Rajesh Subraya Aiyandra
  • Patent number: 10790746
    Abstract: The present disclosure provides a DC-DC switching converter architecture that utilizes the chip's thermal capacity effectively by implementing adaptive switching frequency scaling over the operation region, keeping the die/package temperature constant. The power budget is effectively utilized, and the external components such as capacitors, inductors, and pass device sizes are reduced, thereby increasing the efficiency of the switching converter. An adaptive frequency scalar is optimized, avoiding losses, especially at high loads. The larger the input and output voltage ranges, the bigger the benefit the disclosure becomes.
    Type: Grant
    Filed: August 4, 2017
    Date of Patent: September 29, 2020
    Assignee: Dialog Semiconductor (UK) Limited
    Inventors: Turev Acar, Selcuk Talay
  • Patent number: 10790742
    Abstract: A multi-level power converter and method are presented. The converter provides a ground terminal, an input terminal and an output terminal. It also provides an inductor, a first flying capacitor, a second flying capacitor and a network of switches. The network of switches is driven with a sequence of states including a first state and a second state. In the first state one of the input terminal and the ground terminal is coupled to the output terminal via a first path containing the first flying capacitor and which bypasses the inductor, while the remaining terminal among the input terminal and the ground terminal is coupled to the output terminal via a second path containing the second flying capacitor and the inductor.
    Type: Grant
    Filed: April 17, 2019
    Date of Patent: September 29, 2020
    Assignee: Dialog Semiconductor (UK) Limited
    Inventor: Holger Petersen