Abstract: A method of establishing a low latency connection between a first device and a second device on a wireless network is presented. The method contains the steps of: forming a first wireless connection between the first and second devices; forming at least a second and parallel wireless connection between the first and second devices; and sending data between the first and second devices using at least the first and second connections. For any wireless protocol for data exchange between devices that specifies a minimum interval between data exchange events, the present disclosure enables a lower latency than would otherwise be achievable according to a standard protocol.

Abstract: Methods, structures and computer program products for digital sample rate conversion are presented. An input digital sample with a first frequency is converted to an output sample with a second frequency. A sample rate conversion circuit is provided which provides an enhanced transposed farrow structure that enables an optimised trade-off between noise levels and computational complexity. Each output sample is derived by convolution of a continuous time interpolation kernel with a continuous time step function representing the input sample stream. In a sample rate conversion structure, there is a trade-off between the quality and the computational complexity. The quality is defined as a ratio between the (wanted) signal power and the (unwanted) noise power. The computational complexity may be defined as the average number of arithmetic operations that are required to generate one output sample. A higher computational complexity will generally lead to a higher power consumption and larger footprint.

Abstract: An object of this disclosure is to implement a Buck, Boost, or other switching converter, with a circuit to supply a reference voltage and Adaptive Voltage Positioning (AVP), by a servo and programmable load regulation. The reference voltage is modified, achieving a high DC gain, using a servo to remove any DC offset at the output of the switching converter. The correction implemented by the servo is measured, and a programmable fraction of the correction is injected back on either the reference voltage or the output feedback voltage. To accomplish at least one of these objects, a Buck, Boost, or other switching converter is implemented, consisting of an output stage driven by switching logic, with a servo configured between the reference voltage and the control loops of the Buck converter. The AVP function is implemented on either the reference voltage or output feedback voltage.

Abstract: A circuit for operating a transistor device that acts as a switch is presented. The circuit includes the transistor device and a control circuit coupled to a gate of the transistor device. The control circuit is adapted to selectively apply at least a first voltage level, a second voltage level, and a third voltage level to the gate of the transistor device, wherein the first, second, and third voltage levels are distinct voltage levels. The disclosure further relates to a method of operating a transistor device that acts as a switch. The proposed circuit provides additional gate voltages, by contrast to conventional two-level gate drivers. By appropriate choice of the additional gate voltages, reverse mode conductance losses of the transistor device can be reduced and/or to the Safe Operating Area (SOA) of the transistor device can be improved.

Abstract: The present document describes a digital power amplifier configured to provide an amplified output signal at an output port based on an input signal. The power amplifier comprises a drive unit configured to generate a high side drive signal comprising a sequence of pulses for controlling the high side switch and a low side drive signal comprising a sequence of pulses for controlling the low side switch, respectively. The drive signals are generated such that the pulses of the high side drive signal are non-overlapping with regards to the pulses of the low side drive signal, and such that the sequence of pulses of the high side drive signal and the sequence of pulses of the low side drive signal have a reduced fraction of energy from higher order harmonics compared to a sequence of rectangular shaped pulses.

Abstract: A flyback converter control architecture is provided in which primary-only feedback techniques are used to ensure smooth startup and detection of fault conditions. During steady-state operation, secondary-side regulation is employed. In addition, current limits are monitored during steady-state operation using primary-only feedback techniques to obviate the need for a secondary-side current sense resistor.

Abstract: Current in a switching converter is controlled using a current-mode hysteretic controller. The high-side switch (usually a PMOS) is turned off when the current in the coil exceeds a certain peak control current. The low-side switch (usually an NMOS) is turned off when the current in the coil falls below a certain valley control current. A current ramp is added to one of these control currents, either peak or valley. The current ramp is initiated by a reference clock signal, which has the effect of synchronizing the switching converter to the reference clock.

Abstract: A method of synchronizing the clocks of a master device and at least a first slave device which are connected on a wireless network. The method includes sending a scan command from the master device to at least the first slave device, setting the master device to a broadcast mode and broadcasting data, the broadcast data comprising a first time stamp; scanning the broadcasting data at at least the first slave device and resetting the clock of the first slave device using the first time stamp. In particular, but not exclusively, the present disclosure relates to synchronizing the clocks of two devices which are connected on a Bluetooth Low Energy (BLE) wireless network.

Abstract: A wired connection, such as USB-C, for charging a sink from a source, has a configuration channel and a power transmission channel. The presence of data on the configuration channel is used to determine that a cable has been disconnected from the power source. This charging system contains a capacitive power converter and a controller for controlling the capacitive power converter. There is also a configuration channel detector, which is arranged to detect the status of the configuration channel and to provide this status to the controller, so that the system can determine that the source has been detached from the bus when no configuration channel data is present.

Abstract: A digital voltage regulator and a method to regulate an output voltage at an output node based on an input voltage is presented. The regulator has a driver stage with N driver slices, with N>1. Each of the N driver slices can be activated or deactivated individually. A driver slice comprises a current source to provide an output current component to the output node, if the driver slice is activated. Furthermore, the regulator has a control unit to activate a number n of the N driver slices, based on a deviation of a feedback voltage from a reference voltage, where the feedback voltage is dependent on the output voltage.

Abstract: A power supply has a multi-level DC-DC converter and a battery pack with two or more cells provided in series. The switching DC-DC converter provides a regulated voltage at an output. The converter has an energy storage element. The switching regulator is designed to selectively operate in two or more different modes. It switches between a first mode where one cell is connected (between battery and inductor of the converter), and the converter functions like a single cell buck converter and a second mode where two cells are connected in series and the converter functions like a two series cell buck converter. In general, any number of cells and modes can be provided, with successive cells being connected in series in each mode.

Abstract: This disclosure relates to an analog-to-digital converter, ADC.

Abstract: The embodiments disclosed herein describe a set of fault detection circuits for LED circuits in an LED channel. A first fault detection circuit is configured to detect a short fault across one or more LEDs. A second fault detection circuit is configured to detect an open fault across an LED. A third fault detection circuit is configured to detect a short across an LED channel transistor. A fourth fault detection circuit is configured to detect an LED channel sense resistor open fault. A fifth fault detection circuit is configured to detect if the LED channel is being intentionally unused. These fault detect circuits can be implemented in a fault detection integrated circuit coupled to the LED channel.

Abstract: A power combiner for an outphasing amplifier system comprises an output terminal, a first input terminal, a first inductor, and a first capacitor, wherein the first input terminal is connected to ground via the first inductor and the first input terminal is connected to the output terminal via the first capacitor. The power combiner further comprises a second input terminal, a second capacitor, and a second inductor, wherein the second input terminal is connected to ground via the second capacitor and the second input terminal is connected to the output terminal via the second inductor. The first capacitor can have a same capacitance as the second capacitor and the first inductor has a same inductance as the second inductor.

Abstract: An actuation system is proposed for an optical system, comprising a voice coil motor for actuating the optical system, the voice coil motor comprising a magnet and an electric coil, a position measuring unit for measuring the position of the electric coil and providing a position feedback signal, and a control unit for closed loop control of the position of the optical system based on a target position and the position feedback signal, used for generating a drive signal for the electric coil. According to the disclosure, a ferromagnetic element is arranged in proximity to the electric coil so that the inductance of the electric coil depends on its position. Further, the position-measuring unit measures the inductance of the electric coil and determines the position of the electric coil based on the determined inductance.

Abstract: A linear charger circuit and method for providing an output current at an output node is presented. The circuit contains a pass device connected between an input node and the output node, first and second replica devices connected in parallel to the pass device, with their control terminals coupled to a control terminal of the pass device. The first replica device is coupled to a first circuit path for determining whether current output by the linear charger circuit shall be terminated. The second replica device is coupled to a second circuit path for providing feedback for controlling the pass device, a control circuit coupled to the second circuit path for controlling the pass device based on a quantity indicative of a current flowing through the second circuit path, and a switching circuit coupled to the second circuit path.

Abstract: A bias current generator is disclosed that include an operational amplifier that is self-biased during an inactive period with a bias current to bias a gate of an output transistor. Since the inactive period bias is close to an active period bias applied to the gate of the output transistor during active operation of the bias current generator, the speed of transition from the inactive period to the active period is enhanced by the self-biasing of the operational amplifier.

Abstract: A two-stage power converter is disclosed in which a second stage may command a first stage to adjust an output voltage from the first stage to compensate for PVT variations in the second stage. Alternatively, the second stage may adjust a clocking frequency to compensate for the PVT variations.

Abstract: Driver circuits with S-shaped gate drive voltage curves for ramp-up and ramp-down of power field effect transistors are presented. In ramp-up, the S-shaped curve rapidly ramps the gate voltage of the power FET to its threshold. This ramp-up is self-terminating. The gate voltage of the power FET is slewed through saturation with a time constant. After a predetermined time, the gate of the power FET is driven to approach the supply voltage level. In ramp-down, the S-shaped curve rapidly ramps the gate voltage of the power FET down to its threshold voltage. This ramp-down is self-terminating. The gate voltage of the power FET is slewed through saturation. The gate-source voltage of the power FET is rapidly ramped down to zero. Such S-shaped curves for the gate drive signal allow the control of the transition times of the gate drive signal to acceptable levels of voltage/current spikes and electromagnetic interference.

Abstract: A digital active diode circuit for letting current pass in one direction and substantially blocking current in the opposite direction is presented. The circuit contains switching means comprising an array of switches, a first comparison unit coupled to the digital active diode circuit input and output. The first comparison unit updates its output if the difference between their inputs is higher than a first threshold voltage, and a second comparison unit being coupled to the digital active diode circuit output and input. The second comparison unit updates its output if the difference between its inputs is lower than a second threshold voltage. The switching means switches on or off at least one switch based on the comparisons performed by the first comparison unit and the second comparison unit and wherein the first threshold voltage is different from the second threshold voltage.