Abstract: A current mirror circuit comprising an input driver connected to a plurality of output driver circuits through a current mirror network. The current mirror network is separated into two parts, wherein the first part comprises the input driver circuit and the second part comprises capacitive loads including a filter capacitor. A switch separates the two parts where an amplifier senses the first part and controls the second part to track the first part when the current mirror circuit is activated. The low source resistance of the output of the amplifier facilitates a fast charging of the capacitance of the second part of the current mirror network dramatically improving signal delay and transition time.

Abstract: An infrared signal generator with an interface for receiving an encoded infrared command; and protocol generation circuitry for generating a bitstream that comprises one or more data words that comprise data to be transmitted and one or more protocol words that describe symbols of an infrared protocol is presented. Optionally, the protocol generation circuitry comprises a first circuit for generating a data word and a second circuit for generating a protocol word. Optionally, the infrared signal generator comprises a carrier frequency generator which is selectively combined with the output of either the first circuit or the second circuit to provide a drive signal for an infrared transmitter.

Abstract: The present document relates to power converters. In particular, the present document relates to the protection of the power switches of power converters. A controller configured to control a switched-mode power converter is described. The controller comprises a control pin for controlling a state of a power switch of the switched-mode power converter using a control signal; and a sensing pin for receiving a sensed current signal indicative of a current through the power switch. The controller is configured to detect a break-through situation of the power switch based on the state of the power switch and based on the sensed current signal.

Abstract: Systems and methods of recording real-time video transactions between computerized user devices that make more efficient use of the systems' computing resources. Such systems and methods can record real-time video transactions between computerized user devices (e.g., customer client devices, customer service agent devices) by exploiting similarities between (1) video frame data generated by the respective computerized user devices, and (2) video frame data composed by the systems that record the real-time video transactions, without substantially degrading the video quality of the recorded real-time video transactions.

Abstract: A buck converter device with a zero-cross comparator with an adaptive threshold. The buck converter comprises of a control block that controls a first p-channel MOSFET switch, and a second n-channel MOSFET switch. The p-channel MOSFET switch and the n-channel MOSFET switch provide a sense signal utilizing parasitic bipolar junction transistors. The p-channel MOSFET provides a sense current for the pnp parasitic bipolar junction transistor, The n-channel MOSFET provides a sense current for the npn parasitic bipolar junction transistor. The sense current is stored on a capacitor, and establishes an adaptive offset adjustment to a zero-cross comparator.

Abstract: A method of monitoring a process of powering a portable device through a cable connected between a power supply and a portable device is presented. The method includes applying a time-dependent current variation to one end of the cable in accordance with a spreading sequence, detecting a time-dependent voltage variation at the one end of the cable, the time dependent voltage variation resulting from the applying of the time-dependent current variation, and determining a quantity indicative of an impedance of the cable assembly based on the time-dependent voltage variation and the spreading sequence. Further, an apparatus for monitoring a process of powering a portable device through a cable connected between a power supply and a portable device is presented.

Abstract: An adaptive duty cycle limiting circuit is used with a switching DC-to-DC converter for preventing the duty cycle entering a region of operation having negative gain. The adaptive duty cycle limiting circuit includes a duty cycle ramp signal generator, a voltage source for providing a voltage having a fractional value of an input voltage source, and a comparator that compares the duty cycle ramp signal with the fractional value of the input voltage source. When the voltage level of the duty cycle ramp signal is less than the fractional value of the voltage source, a cycle limit signal is activated and communicated to a switching control circuit to adjust the duty cycle of the switching DC-to-DC converter to prevent the duty cycle entering the region of operation where the gain of the switching DC-to-DC converter becomes negative.

Abstract: A switching DC-to-DC converter has an adaptive duty cycle limiting circuit with an inductor current sensor to generate a sense signal indicative of magnitude of the inductor current. A replica signal is generated from the sense signal and transferred through a replica parasitic resistance circuit. A differential voltage is developed across the replica parasitic resistances and compared with a maximum limit voltage level. The maximum limit voltage level is indicates that a gain level of the switching DC-to-DC converter has decreased even though the duty cycle has increased. A duty cycle limit signal is generated and transferred to disable a switch in a switching circuit for limiting the duty cycle of the switching DC-to-DC converter, when the gain level has decreased such that the switching DC-to-DC converter does not enter a region where the gain of the switching DC-to-DC converter has a negative slope.

Abstract: Measurement circuits which are configured to measure wide ranges of the input voltage using a sensed input voltage of the driver circuits for solid state lighting (SSL) devices are presented. The measurement circuit comprises a first resistor which is coupled at a first side to the input voltage. The measurement circuit comprises current mirror circuitry coupled at an input to a second side of the first resistor, and which translates an input current at the input of the current mirror circuitry into an output current at an output of the current mirror circuitry, such that the output current is proportional to the input current by a current mirror ratio. The measurement circuit comprises a second resistor coupled to the output of the current mirror circuitry and to provide the sensed input voltage, when the input voltage is coupled to the first side of the first resistor.

Abstract: A facsimile transmission device implements silence suppression based on a state of a facsimile call and detected facsimile signals. A decision process implemented in the facsimile device can determine when silence suppression should be enabled. The facsimile device may be an IP media gateway connected between a PSTN and an IP network, or may be an IP endpoint. The determination of when to enable silence suppression can be based on the state of sending or receiving facsimile transmissions including facsimile operations and/or signaling. The decisions can be based on the type of facsimile transmission including G3 type or SG3 type facsimile transmissions. By enabling silence suppression during facsimile transmissions, significant reductions in bandwidth requirements can be achieved for the facsimile transmission while maintaining facsimile transmission quality.

Abstract: An LED lamp comprises one or more LEDs and an LED driver receiving an input signal from a dimmer switch indicative of an amount of dimming for the LED lamp. The LED driver controls regulated current through the one or more LEDs based on the input signal such that an output light intensity of the one or more LEDs substantially corresponds to the amount of dimming for the LED lamp. A regulated output provides operating power for the LED driver. A controller regulates the regulated output to power the LED driver. The controller selects a power source for charging the regulated output from two or more power sources, and the regulated output is charged using the power source selected by the controller.

Abstract: A switch mode power supply, which functions in a continuous current mode and a discontinuous mode employing a zero crossing control circuit for determining a polarity of an inductor current and from the polarity of the inductor current, controlling an operational state of a switching section of the switch mode power supply such that the inductor current becomes approximately zero amperes at the end of each demagnetization phase of operation.

Abstract: An electronic circuit is disclosed for dividing the frequency of a periodic signal, wherein at least one of the memory elements is arranged with its output terminal connected to the input terminal of another memory element wherein the electronic circuit is configured to generate an output signal having a smaller fundamental frequency than the clock signal at at least one of the output terminals. Each memory element is configured to change and hold a voltage at the output terminal based on a voltage at the input terminal at times controlled by a clock signal received at the clock terminal. At least two of the memory elements are stacked in the sense that the bottom terminal of a first memory element is connected to the top terminal of a second memory element to enable the charge to flow from the first memory element to the second memory element.

Abstract: The present document relates to multi-stage amplifiers, such as linear regulators (e.g. low-dropout regulators). A method and a circuit for reducing leakage current of such multi-stage amplifiers is presented. A voltage regulator is described. The voltage regulator comprises a pass device configured to provide a load current at a regulated output voltage to an output node of the voltage regulator. A source of the pass device is coupled to a first potential of the voltage regulator. Furthermore, the voltage regulator comprises drive circuitry configured to control the pass device via a gate of the pass device, based on a reference voltage and based on a feedback voltage derived from the output voltage. In addition, the voltage regulator comprises leakage reduction circuitry configured to pull-up the gate of the pass device using a second potential; wherein the second potential is higher than the first potential.

Abstract: A switching mode power supply (SMPS) is capable of clearing an overvoltage condition. The overvoltage is determined by detecting that the output voltage has exceeded the input voltage by a limited amount. The overvoltage is cleared by repetitively turning on and then off the switches controlling the flow of energy to the SMPS in sequence until the excess charge resulting from the overvoltage is couple to circuit ground, and the output is reduced to within acceptable limits.

Abstract: An arbitrary alignment is provided for a series of pulses controlling a switch that in turn controls a current in an LED. Each pulse is generated according to a target time responsive to a reference time in a corresponding cycle of a synchronization clock. Each pulse has a leading portion that precedes its target time and a trailing portion subsequent to its target time. The arbitrary alignment defines the relative size of the leading portion to the trailing portion such that these relative sizes are incrementally changed across successive ones of the pulses.

Abstract: Amplifiers, notably multi-stage amplifiers, such as linear regulators (e.g. low-dropout regulators) configured to provide a constant output voltage subject to load transients are presented. An amplifier is described, which comprises a first amplification stage configured to provide an intermediate voltage, based on an outer feedback voltage and based on a reference voltage. Furthermore, the amplifier comprises an output stage configured to provide a load current at an output voltage based on the intermediate voltage. In addition, the amplifier comprises an outer feedback circuit configured to derive the outer feedback voltage from the output voltage. The output stage comprises a buffer configured to provide a drive voltage based on the intermediate voltage and based on an inner feedback voltage derived from the output voltage. The buffer comprises a pass device which is configured to provide the load current at the output voltage based on the drive voltage.

Abstract: An apparatus and method for a system with improved power supply rejection ratio (PSRR) over a wide frequency range. The improved PSRR is achieved by negating the influence of the parasitic capacitance associated with the bias lines and the introduction of a regulated power supply with embodiments associated with providing a ripple free and regulated supply. With reduction of parasitic capacitance, and providing an ENABLE switch by a pre-regulated supply, the degradation of the PSRR is achieved. The embodiments include both n-channel and p-channel MOSFETs implementations, and a positive and negative regulated power supply voltage. With the combined influence of the utilization of the VREG supply, and the lowering of battery-to-bias line capacitance using design layout and improved floor planning an improved PSRR over a wide frequency distribution is achieved.

Abstract: A memory circuit for storing a power failure event is presented. When a device restarts after a power supply failure, it usually resets its logic. This prevents the user from retrieving information relating to the power failure. The memory circuit comprises an input to receive a logic signal and an output to issue a logic value. The memory circuit also comprises a plurality of logic elements arranged such that upon powering the memory circuit, the output logic value has a greater probability of settling to a first logic value than a second logic value. Optionally, there is at least one memory element which comprises a first input and an output to issue a memory element logic value, wherein the memory element is operable between a first state in which the memory element logic value is zero and a second state in which the memory element logic value is one.

Abstract: An automatic calibration of a clock of a wireless portable part with respect to a clock of a fixed part in a field environment. The calibration performed in the field environment negates the need to calibrate the clock during manufacture and negates the need for an initial field recalibration because of temperature differences between manufacture and the field. In performing the calibration the frequency of the clock of the portable part is varied until the portable part is synchronous with the fixed part to with in a range of timing bits. The portable part is declared calibrated after remaining calibrated for a defined number of data frames.