Abstract: According to the embodiment, an optical inspection method for a surface state of a subject includes acquiring and discriminating. The acquiring includes acquiring a color vector of a color corresponding to a wavelength spectrum in a color coordinate system of n dimensions (n is a natural number equal to or larger than 1), which is equal to or smaller than a number of a plurality of color channels of pixels of an image sensor, with optical imaging using a wavelength spectrum selection portion that selectively allows a plurality of wavelength spectra different from one another from a surface of the subject to pass. The discriminating includes discriminating the surface state of the subject based on a direction of the color vector in the color coordinate system.

Abstract: Provided is an apparatus for image fusion, including: an image sensor, a light compensator, a light filter assembly, and an image processing unit, the image sensor being on a light output side of the light filter assembly; wherein the image sensor is configured to generate and output a first image signal and a second image signal through a plurality of exposures; the light compensator comprises a first light compensation apparatus configured to perform near-infrared light compensation; the light filter assembly comprises a first light filter; and the image processing unit is configured to acquire a fused image by processing the first image signal and the second image signal.

Abstract: Various illustrative aspects are directed to a data storage device comprising a disk, a read/write head configured to read data from and write data to the disk, a laser diode (LD) coupled to a nearfield transducer configured to heat an area of the disk near the read/write head, a first resistive temperature detector (RTD), a second RTD, and one or more processing devices configured to: apply a laser bias to the LD during a write operation; obtain a plurality of differential signal measurements, based at least in part on a plurality of measurements from each of the first and second RTDs; and adjust the laser bias applied to the LD, based at least in part on comparing the plurality of differential signal measurements to a target value for the differential signal.

Abstract: A data storage device may include a media comprising a magnetic recording layer and a heat-assisted magnetic recording (HAMR) head for writing to the magnetic recording layer, the HAMR head comprising: a waveguide, a main pole comprising a main-pole surface facing the magnetic recording layer, a near-field transducer (NFT) situated between the main pole and the waveguide, and a transparent overcoat. The NFT comprises a main body and a micropillar. The micropillar comprises a micropillar surface facing the magnetic recording layer. A first distance between the micropillar surface and the media is less than a second distance between the main-pole surface and the media. The transparent overcoat is situated on the main-pole surface and the micropillar surface.

Abstract: A closed-loop service, referred to as an Adaptive Data Analytics Service (“ADAS”), characterizes the performance of a system or systems by providing information describing how users or agents are operating the system, how the system components interact, and how these respond to external influences and factors. The ADAS then builds models and/or defines relationships that can be used to optimize performance and/or to predict the results of changes made to the system(s). Subsequently, this learning provides the basis for administering, maintaining, and/or adjusting the system(s) under study. Measurement can be ongoing, even after the operating parameters or controls of a system under the administration or monitoring of the ADAS have been adjusted, so that the impact of such adjustments can be determined.

Abstract: The present disclosure is generally related to a magnetic recording device comprising a magnetic recording head. The magnetic recording head comprises a main pole, a shield, and a spintronic device disposed between the main pole and the shield. The spintronic device comprises two field generation layers (FGLs), two spin polarization layers (SPLs), and two spin kill layers. The spintronic device further comprises one or more optional thin negative beta material layers, such as layers comprising FeCr, disposed in contact with at least one of the spin kill layers. When electric current is applied, the spin kill layers and optional negative beta material layers eliminate or reduce any spin torque between the FGLs and the SPLs.

Abstract: An AC/DC converter stage for a converter system with an input series structure. The AC/DC converter stage includes two input terminals for inputting an AC input voltage and at least a first circuit branch with at least two switches that are electrically connected in series at a first connection point, where a first input terminal of the two input terminals is electrically connected to the first connection point of the first circuit branch. At least one first electrical storage provides a DC output voltage and is electrically connected in parallel to the first circuit branch. At least one controllable bidirectional switch is electrically connected between the two input terminals.

Abstract: The multi-temperature control cabinet includes a cabinet body, a cabinet door, and a refrigerating system. The refrigerating system includes at least one air conditioner, at least one direct ventilation unit, and an environment monitoring apparatus. Both the air conditioner and the direct ventilation unit are disposed on the cabinet door, and the air conditioner and the direct ventilation unit are disposed in parallel in a height direction of the cabinet door. An air guide assembly is disposed between the direct ventilation unit and an air exhaust vent of the air conditioner. The environment monitoring apparatus is connected to both the air conditioner and the direct ventilation unit, and the environment monitoring apparatus is configured to monitor temperature and humidity in the cabinet body, and control turning-on and turning-off of the air conditioner and the direct ventilation unit based on the temperature and the humidity in the cabinet body.

Abstract: Systems, methods, and apparatuses for providing dynamic, prioritized spectrum utilization management. The system includes at least one monitoring sensor, at least one data analysis engine, at least one application, a semantic engine, a programmable rules and policy editor, a tip and cue server, and/or a control panel. The tip and cue server is operable utilize the environmental awareness from the data processed by the at least one data analysis engine in combination with additional information to create actionable data.

Abstract: A system includes at least one memory controller that partitions at least one memory into a plurality of nodes. Blast zones are formed that each include a predetermined number of nodes. Cache lines are erasure encoded to be stored in one or more blast zones with at least two nodes in a blast zone storing respective portions of a cache line and at least one node in the blast zone storing a parity portion. In one aspect, it is determined that data stored in one or more nodes of a blast zone needs to be reconstructed and stored in one or more spare nodes designated to replace the one or more nodes. Erasure decoding is performed using data from one or more other nodes in the blast zone to reconstruct the data for storage in the one or more spare nodes.

Abstract: Methods for tracking a signal origin by a spectrum analysis and management device are disclosed. Signal characteristics of other known emitters are used for obtaining a position of an emitter of a signal of interest. In one embodiment, frequency difference of arrival technique is implemented. In another embodiment, time difference of arrival technique is implemented.

Abstract: Systems, methods, and apparatuses for providing optimization of network resources. The system is operable to monitor the electromagnetic environment, analyze the electromagnetic environment, and extract environmental awareness of the electromagnetic environment. The system extracts the environmental awareness of the electromagnetic environment by including customer goals. The system is operable to use the environmental awareness with the customer goals and/or user defined policies and rules to extract actionable information to help the customer optimize the network resources.

Abstract: Devices and methods enable optimizing a signal of interest based on identifying and analyzing the signal of interest based on radio frequency energy measurements. Signal data is compared with stored data to identify the signal of interest. Signal degradation data is calculated based on noise figure parameters, hardware parameters and environment parameters. The signal of interest is optimized based on the signal degradation data. Terrain data is also operable to be used for optimizing the signal of interest.

Abstract: Systems, methods, and apparatuses for providing dynamic, prioritized spectrum utilization management. The system includes at least one monitoring sensor, at least one data analysis engine, at least one application, a semantic engine, a programmable rules and policy editor, a tip and cue server, and/or a control panel. The tip and cue server is operable utilize the environmental awareness from the data processed by the at least one data analysis engine in combination with additional information to create actionable data.

Abstract: A non-volatile memory system tests for a voltage leak in any of multiple planes using a voltage being ramped up on selected word lines in the multiple planes. If no voltage leak is detected, then the system concurrently programs data into memory cells connected to the selected word lines in the multiple planes. If a voltage leak is detected in any of the planes, then the system separately tests each plane for the voltage leak at its respective selected word line in order to determine which plane is the source of the voltage leak, and then concurrently programs data into memory cells connected to the selected word lines in planes without the detected voltage leak while isolating the plane with the detected voltage leak.

Abstract: Technology is disclosed herein for detecting evolved bad blocks in three-dimensional NAND. The test may include a drain side erase that includes applying an erase voltage from the bit lines and a source side erase that includes applying an erase voltage from the source line(s). If the source side erase performed worse than the drain side erase this may indicate a defect near the source side of the block. For example, the source side erase may fail but the drain side erase may pass. As another example the source side erase may take at least a pre-determined number of additional erase pulses to pass than the drain side erase. If the block is found as having a defect the entire block could be marked bad or the defective region could be identified such that the defective region is no longer used.

Abstract: A semiconductor device includes a drain, a substrate, an epitaxial layer, and a semiconductor layer. The semiconductor layer includes a source region located on a side the semiconductor layer away from the epitaxial layer. A trench extending to the epitaxial layer is disposed on a side of the source region is away from the epitaxial layer. A gate, an electrode plate, a first shield gate, and a second shield gate are disposed in the trench. The electrode plate is located between the first shield gate and the second shield gate. The trench is further filled with an oxidized layer structure. The first shield gate and the second shield gate are separately spaced from the electrode plate to form electrode plate capacitance. One of the source region, the drain, and the gate is electrically connected to the electrode plate a first electrode, and a second one of the source region, the drain, and the gate is electrically connected to the shield gate structure.

Abstract: The memory device includes a memory block with a plurality of memory cells that are arranged in a plurality of word lines. The memory device also includes circuitry that is configured to program at least some of the plurality of memory cells of a selected word line of the plurality of word lines in at least one program loop of a programming operation. During the at least one program loop, the circuitry is configured to apply a programming pulse to the selected word line, perform a verify operation, and perform an analog bitscan operation. The circuitry is also configured to determine an output of the analog bitscan operation. The output is one of at least three options. The circuitry is further configured to control at least one programming parameter based on the output of the analog bitscan operation.

Abstract: The memory device includes a plurality of memory cells that are arranged in word lines, including a selected word line. Circuitry is configured to program at least some of the plurality of memory cells of the selected word line in at least one program loop of a programming operation. During the at least one program loop, the circuitry is configured to apply a programming pulse to the selected word line, perform a verify operation, and perform an analog bitscan operation. The circuitry is further configured to determine an output of the analog bitscan operation, the output being one of at least three options. The circuitry is also configured to control at least one programming parameter based on the output of the analog bitscan operation. The at least one programming parameter is an early program-verify termination parameter or a smart verify parameter.

Abstract: The memory device includes a memory block with a plurality of memory cells that are arranged in a plurality of word lines. Circuitry is configured to program at least some of the plurality of memory cells in a program loop or that is configured to erase at least some of the plurality of memory cells in an erase loop. During the program loop or the erase loop, the circuitry is configured to perform a verify operation and an analog bitscan operation. In the analog bitscan operation, the circuitry counts the memory cells that pass or that fail the verify operation. The circuitry is also configured to determine an output of the analog bitscan operation, the output being one of at least three options.