Abstract: Identifying recording disk defects in a data storage device such as a hard disk drive (HDD), for which disk defects are not previously identified, includes responsive to a first user data write request to a particular storage area of a disk medium, writing the user data to the particular storage area, reading the written user data from the particular storage area, and verifying the integrity of the user data read from the particular storage area. Upon passing, a second user data write request to the same particular storage area can be fulfilled without again reading and verifying. Upon failing, the particular storage area is marked as defective and the user data is written to a different storage area. This procedure can be repeated in response to each initial user write request to each storage area of each disk medium, foregoing the need for disk surface scanning during manufacturing.
Abstract: A HAMR data storage device may include a magnetic media and a slider comprising: a main pole, a waveguide, and a near-field transducer (NFT) situated between the main pole and the waveguide, wherein an air-bearing surface (ABS) of the slider comprises a transparent overcoat layer situated over the main pole, the waveguide, and the NFT, and wherein the transparent overcoat layer has a particular thickness such that, during an operational phase of the HAMR data storage device, a gap between a media-facing surface of the transparent overcoat layer and the magnetic media is less than about 0.5 nm.
Abstract: Systems, methods and apparatus are disclosed for automatic signal detection in an RF environment. An apparatus comprises at least one receiver and at least one processor coupled with at least one memory. The apparatus is at the edge of a communication network. The apparatus sweeps and learns the RF environment in a predetermined period based on statistical learning techniques, thereby creating learning data. The apparatus forms a knowledge map based on the learning data, scrubs a real-time spectral sweep against the knowledge map, and creates impressions on the RF environment based on a machine learning algorithm. The apparatus is operable to detect at least one signal in the RF environment.
Type:
Grant
Filed:
April 12, 2024
Date of Patent:
December 3, 2024
Assignee:
Digital Global Systems, Inc.
Inventors:
David William Kleinbeck, Ronald C. Dzierwa, Daniel Carbajal
Abstract: Systems, methods, and apparatuses for providing dynamic, prioritized spectrum utilization management. The system includes at least one monitoring sensor, at least one data analysis engine, at least one application, a semantic engine, a programmable rules and policy editor, a tip and cue server, and/or a control panel. The tip and cue server is operable utilize the environmental awareness from the data processed by the at least one data analysis engine in combination with additional information to create actionable data.
Type:
Grant
Filed:
August 6, 2024
Date of Patent:
December 3, 2024
Assignee:
Digital Global Systems, Inc.
Inventors:
Armando Montalvo, Dwight Inman, Edward Hummel
Abstract: In an automatic test system, a test computer of a kind of test equipment communicates with a loading-and-unloading computer of a kind of loading-and-unloading equipment. The loading-and-unloading equipment automatically loads a plurality of target devices on a plurality of test carriers according to the state of the test equipment, and the test equipment automatically tests the target devices loaded on the test carriers according to the state of the loading-and-unloading equipment. In addition, after the test is completed, the loading-and-unloading equipment automatically unloads the tested target devices from the test carriers, and automatically sorts the tested target devices according to the test results generated by the test equipment.
Abstract: A power supply system, a converter, and a circulating current suppression method of the converter. The power supply system includes at least two converters that are coupled between a direct current power supply and an alternating current grid. Each converter obtains target output reactive power when an output current of the converter starts to increase from an initial current, obtains a reactive power compensation parameter based on the three-phase output voltages. Further, each converter obtains compensated output reactive power of the converter based on the reactive power compensation parameter and adjusts actual output reactive power of the converter based on the target output reactive power and the compensated output reactive power, so that an absolute value of a difference between common-mode output voltages of any two of the at least two adjusted converters is less than a difference threshold.
Type:
Grant
Filed:
October 12, 2022
Date of Patent:
December 3, 2024
Assignee:
Huawei Digital Power Technologies Co., Ltd.
Inventors:
Xinyu Yu, Yuan Yao, Fuqiang Xu, Kai Xin
Abstract: Systems, methods, and apparatuses for providing dynamic, prioritized spectrum utilization management. The system includes at least one monitoring sensor, at least one data analysis engine, at least one application, a semantic engine, a programmable rules and policy editor, a tip and cue server, and/or a control panel. The tip and cue server is operable utilize the environmental awareness from the data processed by the at least one data analysis engine in combination with additional information to create actionable data.
Abstract: In some situations, the programming of one memory die can be suspended in favor of the programming of another memory die. This can lead to a delay in certain programming operations. To avoid this problem, a data storage device can perform dynamic logical page write ordering by determining an availability of each memory die of a plurality of memory dies and changing a programing order of the plurality of memory dies in response to the determined availability.
Type:
Application
Filed:
July 21, 2023
Publication date:
November 28, 2024
Applicant:
Western Digital Technologies, Inc.
Inventors:
Noor Mohamed AA, Ramanathan Muthiah, Subash Rajaram
Abstract: A gemstone appraisal system. The system may include a server accessible via a network, the server including a pricing application, a pricing algorithm, a pricing GUI, controller, operating memory, and a communications interface. The system may further include a data store in communication with the server; and one or more data sources, accessible to the pricing application via the network. The controller may be configured to execute stored program instructions, including providing access to a user; receiving gemstone data related to a subject gemstone; querying one or more data sources for pricing information of gemstones having the same characteristics as the subject gemstone; analyzing the query results and calculating in real-time pricing data for the subject gemstone, the pricing data may include historical, dealer, and/or retail price data, and/or a buy price for the subject gemstone; and generating a price report for the subject gemstone.
Abstract: Technology is disclosed for a current source for reading a memory cell having a threshold switching selector. The current source may be operated in a first mode when turning on the threshold switching selector and in a second mode when sensing a voltage across the memory cell. The first mode may allow the use of the full range of the power supply voltage, which provides sufficient voltage across the memory cell to turn on the threshold switching selector. In the second mode the magnitude of the read current is less dependent on the voltage across the memory cell. The second mode therefore provides for accurate sensing of the memory cell. The first mode may also be used when writing the memory cell, which provides sufficient voltage across the memory cell to write the memory cell.
Type:
Application
Filed:
July 27, 2023
Publication date:
November 28, 2024
Applicant:
Western Digital Technologies, Inc.
Inventors:
Christopher J. Petti, Ward Parkinson, Thomas Trent, James O'Toole
Abstract: A memory device includes a memory block comprising a plurality of memory cells and control circuitry configured to perform a read level acquisition operation to determine optimal read levels for reading a plurality of data states of the plurality of memory cells. To perform the read level acquisition operation, the control circuitry is configured to supply a read level acquisition waveform to the plurality of memory cells, obtain data miss compare (DMC) values for the plurality of memory cells based on the read level acquisition waveform, and identify the optimal read levels for the plurality of data states based on the DMC values. The control circuitry is further configured to perform a read operation on the plurality of memory cells in accordance with the optimal read levels as identified based on the DMC values.
Abstract: Systems, methods, and apparatuses for providing dynamic, prioritized spectrum utilization management. The system includes at least one monitoring sensor, at least one data analysis engine, at least one application, a semantic engine, a programmable rules and policy editor, a tip and cue server, and/or a control panel. The tip and cue server is operable utilize the environmental awareness from the data processed by the at least one data analysis engine in combination with additional information to create actionable data.
Abstract: A server includes at least one local memory and communicates with one or more network devices that provide an external shared memory. A kernel space of the server is used to monitor memory usage by different applications executed by the server. A memory kernel module adjusts usage of the at least one local memory and the external shared memory by the different applications based at least in part on the monitored memory usage. In another aspect, a memory access profiling server receives memory information and application usage information added to packets sent between servers and one or more memory devices. The memory access profiling server analyzes the memory information and application usage information to determine memory placement information that is sent to at least one server to adjust usage of the external shared memory.
Abstract: An inverter includes an inverter circuit, a collection circuit, a balanced circuit, and an inductor. The collection circuit is configured to detect a direct current bus voltage, to obtain end voltage values of a first capacitor and a second capacitor. The balanced circuit is configured to: when an end voltage value of a target capacitor is less than or equal to a first voltage threshold, control on or off of a plurality of switching transistors, to adjust a current for charging the target capacitor through the inductor and reduce a difference between the end voltage values of the target capacitor and a non-target capacitor in the two groups of capacitors. When the difference between the end voltage values of the two groups of capacitors in the inverter circuit is large, the balanced circuit may adjust an output current of the inductor to charge the target capacitor.
Type:
Application
Filed:
August 8, 2024
Publication date:
November 28, 2024
Applicant:
Huawei Digital Power Technologies Co., Ltd.
Inventors:
Shen GAO, Fenglong LU, Shuai LIU, Lei SHI
Abstract: Systems, methods, and apparatuses for providing dynamic, prioritized spectrum utilization management. The system includes at least one monitoring sensor, at least one data analysis engine, at least one application, a semantic engine, a programmable rules and policy editor, a tip and cue server, and/or a control panel. The tip and cue server is operable utilize the environmental awareness from the data processed by the at least one data analysis engine in combination with additional information to create actionable data.
Abstract: Systems, methods, and apparatuses for providing dynamic, prioritized spectrum utilization management. The system includes at least one monitoring sensor, at least one data analysis engine, at least one application, a semantic engine, a programmable rules and policy editor, a tip and cue server, and/or a control panel. The tip and cue server is operable utilize the environmental awareness from the data processed by the at least one data analysis engine in combination with additional information to create actionable data.
Abstract: A memory apparatus and method of operation are provided. The apparatus includes memory cells connected to word lines and configured to retain a threshold voltage corresponding to one of a plurality of data states. A control means ramps up and applies a read voltage to unselected ones of the word lines while applying verification pulses of program verify voltages each associated with one of the plurality of data states to selected ones of the word lines to determine whether the memory cells connected thereto have the threshold voltage above each of the verify voltages associated with the plurality of data states targeted during a program-verify operation. The control means delays ramping of at least one of the selected ones of the word lines and the unselected ones of the word lines by a predetermined period of time in response to the memory apparatus operating in a predetermined mode.
Type:
Application
Filed:
August 2, 2023
Publication date:
November 28, 2024
Applicant:
Western Digital Technologies, Inc.
Inventors:
Abu Naser Zainuddin, Jiahui Yuan, Toru Miwa
Abstract: Systems, methods, and apparatuses for providing dynamic, prioritized spectrum utilization management. The system includes at least one monitoring sensor, at least one data analysis engine, at least one application, a semantic engine, a programmable rules and policy editor, a tip and cue server, and/or a control panel. The tip and cue server is operable utilize the environmental awareness from the data processed by the at least one data analysis engine in combination with additional information to create actionable data.
Type:
Application
Filed:
August 6, 2024
Publication date:
November 28, 2024
Applicant:
Digital Global Systems, Inc.
Inventors:
Armando Montalvo, Dwight Inman, Edward Hummel
Abstract: An apparatus is provided that includes a memory array and a control circuit. The memory array includes non-volatile memory cells each including a resistive random access memory element. The control circuit is configured to receive a read command that specifies an address of a first group of the non-volatile memory cells, use a first predetermined read reference value to perform a first read of the first group of the non-volatile memory cells to provide first read data, while performing the first read, retrieve from a memory a second predetermined read reference value corresponding to the specified address, and in response to a condition being satisfied regarding the first read data, use the second predetermined read reference value to perform a second read of the first group of the non-volatile memory cells to provide second read data.
Type:
Application
Filed:
July 19, 2023
Publication date:
November 28, 2024
Applicant:
Western Digital Technologies, Inc.
Inventors:
Deniz Bozdag, Dimitri Houssameddine, Juan P. Saenz, Mark Lin
Abstract: A memory device is provided and includes a memory block that has a plurality of memory cells that are arranged in a plurality of word lines. The memory device also includes a plurality of word line switch transistors that are electrically coupled with the plurality of word lines, where the plurality of word lines are grouped into a plurality of zones based on a size of a word line switch transistor associated with each word line of the plurality of word lines. The memory device also includes a bitline biasing circuit for providing a negative biasing voltage to a bitline corresponding to a memory cell of the selected word line during programming of the selected word line and the bitline biasing circuit is configured to set a magnitude of the negative biasing voltage based on which zone of the plurality of zones the selected word line is in.
Type:
Application
Filed:
August 3, 2023
Publication date:
November 28, 2024
Applicant:
Western Digital Technologies, Inc.
Inventors:
Wei Cao, Weiyi Li, Dengtao Zhao, Xiang Yang