Abstract: A memory apparatus and method of operation are provided. The apparatus includes memory cells each connected to word lines and disposed in memory holes. The memory holes are arranged in rows comprising strings which are grouped into blocks comprising a first plane and a second plane. A control means is configured to program memory cells of the first plane and the second plane connected to one of the word lines using iterations of a program operation. The control means terminates programming of the first plane prior to completing programming of the first plane in response to determining the first plane programs slower than the second plane by a predetermined number of the iterations of the program operation. The control means adjusts the predetermined number of the iterations based on an additional verify iteration performed on at least some of the memory cells beyond the iterations of the program operation.

Abstract: Systems, methods, and apparatuses for providing dynamic, prioritized spectrum utilization management. The system includes at least one monitoring sensor, at least one data analysis engine, at least one application, a semantic engine, a programmable rules and policy editor, a tip and cue server, and/or a control panel. The tip and cue server is operable utilize the environmental awareness from the data processed by the at least one data analysis engine in combination with additional information to create actionable data.

Abstract: The memory device includes sensing circuitry that senses data in the memory cells of a selected word line. If the memory device is in the first operating mode, the sensing circuitry senses the selected word line with a first sensing process that includes applying a first voltage to a source side of at least one NAND string and ramping at least one voltage applied to the memory block to a target voltage over a first duration. If the memory device is in the second operating mode, the sensing circuitry senses the selected word line with a second sensing process that includes applying a second voltage to the source side of at least one NAND string and ramping the at least one voltage applied to the memory block to the target voltage over a second duration that is greater than or equal to the first duration.

Abstract: Systems and methods for automated unmanned aerial vehicle recognition. A multiplicity of receivers captures RF data and transmits the RF data to at least one node device. The at least one node device comprises a signal processing engine, a detection engine, a classification engine, and a direction finding engine. The at least one node device is configured with an artificial intelligence algorithm. The detection engine and classification engine are trained to detect and classify signals from unmanned vehicles and their controllers based on processed data from the signal processing engine. The direction finding engine is operable to provide lines of bearing for detected unmanned vehicles.

Abstract: Systems, methods, and apparatus are provided for automated identification of baseline data and changes in state in a wireless communications spectrum, by identifying sources of signal emission in the spectrum by automatically detecting signals, analyzing signals, comparing signal data to historical and reference data, creating corresponding signal profiles, and determining information about the baseline data and changes in state based upon the measured and analyzed data in near real time, which is stored on each apparatus or device and/or on a remote server computer that aggregates data from each apparatus or device.

Abstract: A memory device includes a memory block including a plurality of memory cells and control circuitry configured to perform a dummy read operation to transition memory cells of the memory block from a first read condition to a second read condition. To perform the dummy read operation, the control circuitry is configured to, subsequent to performing a programming operation on a selected word line and prior to performing a programming operation on a next word line, supply a first voltage pulse to bias the selected word line and previously programmed word lines in the memory block, and, while supplying the first voltage pulse, supply a second voltage pulse to bias unprogrammed word lines in the memory block including the next word line. The second voltage pulse has a lower magnitude than the first voltage pulse.

Abstract: The memory device includes a memory block with memory cells that are arranged in word lines, some of which are reconfigurable word lines that are dummy word lines when the memory block is operating in a one bit per cell mode and are data word lines when the memory block is operating in a multiple bits per cell mode. Circuitry is configured to program the memory cells of a selected word line. The circuitry determines if the selected word line is a reconfigurable word line. If the selected word line is not a reconfigurable word line, the circuitry programs the memory cells of the selected word line with a first programming scheme. If the selected word line is a reconfigurable word line, the circuitry programs the memory cells of the selected word line with a second programming scheme that is different than the first programming scheme.

Abstract: The present application belongs to the field of chiplet technologies and discloses a method, device and storage medium for request processing under mixed cacheline granules. The method is applied to a processor, where a level 2 cache and a level 1 cache of the processor are integrated into a processor chiplet, and a level 3 cache of the processor is integrated into a fabric chiplet. The method includes: acquiring a level 1 cacheline granule of the level 1 cache and a level 3 cacheline granule of the level 3 cache; determining a cache working mode according to the level 1 cacheline granule and the level 3 cacheline granule; and receiving request information and processing the request information based on the cache working mode.

Abstract: An energy storage apparatus includes a battery control unit, a battery monitor unit, and a plurality of cells. The battery control unit is configured to receive a battery state of health (SoH) value estimation model from cloud device, and the battery monitor unit is configured to obtain an estimated SoH value of a first cell based on a real-time equivalent circuit model parameter of the first cell in the plurality of cells and the battery SoH value estimation model. According to the energy storage apparatus, a battery SoH value is estimated by using an artificial intelligence model, and deep charging and discharging do not need to be performed on a battery, so that the battery SoH value can be accurately obtained in a plurality of application scenarios, and a battery capacity abnormality risk can be identified in advance, thereby improving stability of an energy storage system.

Abstract: A memory device includes memory blocks and control circuitry configured to perform an erase operation to selectively erase selected memory cells of the memory blocks, selectively perform an erase verify operation during or subsequent to the erase operation, and perform an erase verify skip operation in which one or more of the erase verify operations are skipped during the erase operation. To perform the erase verify skip operation, the control circuitry is configured to supply a first erase voltage pulse and supply a second erase voltage pulse subsequent to the first erase voltage pulse, the second erase voltage pulse has a greater magnitude than the first erase voltage pulse, and supplying the second erase voltage pulse includes transitioning from the first erase voltage pulse to the second erase voltage pulse without ramping downward between the first erase voltage pulse and the second erase voltage pulse.

Abstract: A memory device includes control circuitry configured to perform an erase operation to erase memory cells of a memory block and perform an erase verify operation to verify whether the memory cells were sufficiently erased. To perform the erase operation, the control circuitry is configured to supply a first erase voltage pulse, perform the erase verify operation subsequent to supplying the first erase voltage pulse, subsequent to the erase verify operation, supply a first bias voltage to a first one of a plurality of memory strings and a second bias voltage different than the first bias voltage to a second one of a plurality of memory strings, and, while supplying the first and second bias voltages, supply a second erase voltage pulse. The second bias voltage is configured to inhibit the second erase voltage pulse supplied to the memory cells of the second one of the plurality of memory strings.

Abstract: Systems and methods for automated unmanned aerial vehicle recognition. A multiplicity of receivers captures RF data and transmits the RF data to at least one node device. The at least one node device comprises a signal processing engine, a detection engine, a classification engine, and a direction finding engine. The at least one node device is configured with an artificial intelligence algorithm. The detection engine and classification engine are trained to detect and classify signals from unmanned vehicles and their controllers based on processed data from the signal processing engine. The direction finding engine is operable to provide lines of bearing for detected unmanned vehicles.

Abstract: This disclosure provides a control method and apparatus for a power supply circuit, and an electric vehicle. The power supply circuit includes a first switch, three bridge arms, and a motor. Each bridge arm includes a first switching transistor and a second switching transistor. The control method is: when detecting that the direct current power supply stops supplying power, controlling the first switch to be turned off; after the first switch is turned off, controlling a second switching transistor of a first bridge arm, a first switching transistor of a second bridge arm among the bridge arms, and a first switching transistor of a third bridge arm among the bridge arms to be turned on, and providing, by the power battery, a first current to the motor, where the first current controls a torque of the motor. This disclosure is implemented to improve NVH characteristics of the electric vehicle.

Abstract: A memory apparatus and method of operation are provided. The apparatus includes word line switches coupled to word lines connected to memory cells. The word line switches are each configured to retain a switch threshold voltage and selectively connect the word lines to a common driver for supplying voltages thereto during a memory operation. A control means is configured to apply predetermined select block switch voltages to a first set of the word line switches connected to the word lines of a selected block. The predetermined select block switch voltages are based on the memory operation performed. The control means apply a predetermined unselect block switch voltage to a second set of the word line switches connected to the word lines of an unselected block. The predetermined unselect block switch voltage is selected to lower the switch threshold voltage of the word line switches of the second set.

Abstract: Systems, methods, and apparatuses for providing dynamic, prioritized spectrum utilization management. The system includes at least one monitoring sensor, at least one data analysis engine, at least one application, a semantic engine, a programmable rules and policy editor, a tip and cue server, and/or a control panel. The tip and cue server is operable utilize the environmental awareness from the data processed by the at least one data analysis engine in combination with additional information to create actionable data.

Abstract: A storage device is disclosed. The storage device is configured to perform a hybrid erase scheme comprising: performing an erase operation including simultaneously erasing memory cells associated with a block; and performing a stripe erase operation including simultaneously erasing memory cells associated with every other wordline of the block and then simultaneously erasing memory cells associated with remaining wordlines of the block.

Abstract: Systems, methods, and apparatuses for providing dynamic, prioritized spectrum utilization management. The system includes at least one monitoring sensor, at least one data analysis engine, at least one application, a semantic engine, a programmable rules and policy editor, a tip and cue server, and/or a control panel. The tip and cue server is operable utilize the environmental awareness from the data processed by the at least one data analysis engine in combination with additional information to create actionable data.

Abstract: A semiconductor device package includes a substrate and a stack of semiconductor dies positioned on the substrate that includes a first semiconductor die and a second semiconductor die. First and second platforms are positioned on the substrate such that the stack of semiconductor dies is positioned therebetween. First and second through-vias are electrically connected to the substrate and extending through the respective first and second platforms. A first bond wire electrically connects the first through-via to the first semiconductor die, and a second bond wire electrically connects the second through-via to the second semiconductor die. The through-vias may reduce the required length of the bond wires thereby reducing signal noise and the platforms may vertically space the bond wires from one another to prevent electrical short circuits.

Abstract: Systems, methods, and apparatuses for providing dynamic, prioritized spectrum utilization management. The system includes at least one monitoring sensor, at least one data analysis engine, at least one application, a semantic engine, a programmable rules and policy editor, a tip and cue server, and/or a control panel. The tip and cue server is operable utilize the environmental awareness from the data processed by the at least one data analysis engine in combination with additional information to create actionable data.

Abstract: A data storage device and method for optimized refresh are provided. In one embodiment, a data storage device is provided comprising a memory and a controller. The controller is configured to: receive, from a host, an identification of a location in the memory; calculate an estimated time to refresh the location in the memory; send the estimated time to the host; and refresh the location in the memory. Other embodiments are provided, and each of the embodiments can be used alone or in combination.