Abstract: The present invention is directed to a computer apparatus for use in a multiprocessor computer system having a main memory storing a plurality of data items and being coupled to a bus. The bus is operated according to a SNOOPY protocol. The computer apparatus includes a processor and a cache memory coupled to the processor. The cache memory contains a subset of the data items stored in the main memory, for access by the processor and includes a TAG store comprising a plurality of VALID indicators, one VALID indicator for each of the data items currently contained in the cache memory. A bus interface is coupled to the cache memory and is adapted for coupling to the bus. The interface operates according to the SNOOPY protocol to monitor transactions on the bus for write transactions affecting data items of the subset having set VALID indicators and determines the identity of each initiator of a write transaction on the bus affecting a VALID data item of the subset.

Abstract: A computer system includes a processor having a primary cache, and a secondary cache data store, cache tag store, and memory controlled by a memory controller. The cache tag store, secondary cache data store, and memory share a common address bus. The secondary cache data store and the memory share a common data bus. In addition, some of the bits of the address bus are saved and fed directly to the memory. The memory controller provides for pipelined secondary cache accesses, during which a corresponding tag from the cache tag store is compared in the processor against the required memory address to determine if the data is located in the secondary cache. If the data is not in the secondary cache, the memory controller asserts the appropriate signals to obtain the data from memory. Because some of the address bits are fed directly to the memory, the setup time for memory control signals can be satisfied during the comparison of the cache data tag.

Abstract: A method and apparatus for improved access to shared memory of an electronic computing system supporting load.sub.-- linked and store.sub.-- conditional machine operations. Data objects in the shared memory are referenced by root pointers of an object directory of the shared memory. Each data object is associated with a check[0] counter and a check[1] counter. A processor first reads the root pointer and the data object's check[0] counter, then copies the data object to a scratch area of memory associated with that processor, the scratch area also having check[0] and check[1] counters associated therewith. The processor then reads the data object's check[1] counter. If the data object's check[0] and check[1] counters are unequal, the processor performs an exponential "back-off" by waiting for a randomly selected period of time before attempting to access the data object again.

Abstract: A node operating in a network using the International Standard Organization (ISO) High-Level Data Link Control (HDLC) network protocol includes a mechanism for encoding information such that frames including the encoded information can be correctly interpreted by nodes operating in either of the standard 16-bit or 32-bit ISO-HDLC operating modes. The encoding mechanism produces a preliminary frame check sequence by encoding the information in an encoder using a generator polynomial G.sub.48 (x), which is a combination of the generator polynomials G.sub.16 (x) and G.sub.32 (x) which are used to produce frame check sequences for nodes operating in 16-bit or 32-bit modes, respectively. Before the information is encoded, the encoding mechanism sets the encoder to an initial condition using an initializing polynomial I.sub.48 (x). The preliminary frame check sequence is further encoded by adding to it a complementing polynomial C.sub.48 (x). The result is a 48-bit frame check sequence.

Abstract: A data storage system includes a multi-tasking processor which manages a write cache to identify adjacent blocks held in the write cache which are to be included in a next write operation, while at the same time handling data transfer requests from a system host. The processor monitors the write cache and when the cache has fewer than a predetermined number of storage locations free, initiates a block-merge task. The processor then determines which block in the write cache is least recently used and, based on virtual block numbers assigned to the data blocks, identifies the blocks in the write cache which are adjacent to the least recently used block and are within the same chunk as that block. The processor maintains a list of these adjacent blocks and the locations in which the blocks are held in the write cache.

Abstract: A method for providing communication between a plurality of nodes coupled in a ring arrangement, wherein a plurality of the nodes comprise processors each having a cache memory for storing a subset of shared data. Each of the nodes on the ring deposits data into a data slot during a given time period. The data deposited by each node may comprise an address field and a node field. To ensure data coherency between the caches, each processor on the ring includes a queue for saving a plurality of received data representative of the latest bus data transmitted on the bus. As each processor receives new data, the new data is compared against the plurality of saved data in the queue to determine if the address field of the new data matches the address field of any of the saved data of the queue. In the event that the new data matches one of the plurality of saved data, it is determined whether the new data represents updated data from the memory device.

Abstract: Computational requirements are reduced for executing simulation code for a logic circuit design having at least some elements which are synchronously clocked by multiple phase clock signals, the simulation code including data structures associated with circuit modules and nodes interconnecting the circuit modules. The simulation code is preanalyzed and phase waveforms are stored each representing values occurring at a node in successive phases. Based on the preanalysis, modules are categorized in a first category, for which an event-based evaluation is to be performed in each phase of the simulation, and a second category for which no event-based evaluation need be performed in at least one but not all phases. For each phase of a second category module, an appropriate response to an event occurring with respect to the module is determined.

Abstract: An apparatus for sequencing turn-on and turn-off of power converters includes a first DC to DC converter responsive to a control signal for asserting a voltage supply signal and a sense circuit responsive to the output of said first converter to sense the level of voltage at the output of the first converter and to provide an enable signal in response to the output of said first converter when the first converter reaches a desired value. The apparatus further includes a second DC to DC converter responsive to said enable signal to provide a second supply voltage at a second different voltage level. The sequencing control has a circuit responsive to said second supply voltage and the first supply voltage, to short the second DC to DC converter to a reference potential.

Abstract: An implementation efficient interrupt select mechanism which allocates interrupt flags between N interrupt requestors, e.g. communication channels. A multi-channel controller provides the select mechanism with control signals and asserts an interrupt request when a channel, being visited by a scanner, which may be incorporated into the controller, is asserting an interrupt request. If the interrupt flag is available, the number of the channel asserting the request is locked into a latch. The latch remains locked until the interrupt request is cleared, a control signal is received from the controller and the channel being visited by the scanner equals the channel number stored in the latch. The scanner increments from channel to channel regardless of the assertion of the interrupt flag or the locking of the latch. In this manner, a single scanner may be used with any number or interrupt select mechanisms.

Abstract: A semiconductor memory device according to the invention includes a main memory array comprising a plurality of memory sub-arrays. Each of the memory sub-arrays comprises a plurality of columns and at least one redundant column. Each column of the memory sub-array also includes multiplexing means, coupled to the input and output path of the respective column and an input and output path of a neighboring column. In addition, the redundant column is coupled to the input and output path of a neighboring column. In the event that one of the columns of the memory sub-array is defective, the multiplexing means of each of the columns between the defective column and the redundant column acts to couple the input and output paths of that column to the input and output paths of the neighboring column. With such an arrangement, the defective column is bypassed and a memory device capable of operating without defects is provided.

Abstract: In a computer system that embodies a first hardware (X) architecture and includes a memory system and at least one simulator for a second (Y) architecture and a system for executing and debugging multiple codes having an environment manager that handles cross-domain calls, a debugging system and method are provided for debugging code in each domain as part of said multi-code executing and debugging system in a multi-architecture environment. In response to calls for debugging from either the X domain or the Y domain, commands are generated for controlling operations in both domains. User generated RUN and STEP commands control the machine execution state in the domain where debugging is performed. General support commands and debug operations support commands including EXAMINE, DEPOSIT, SET BREAKPOINT and CANCEL BREAKPOINT commands which are implemented differently for the different domains may also be user generated for controlling debugging.

Abstract: A system and method for analyzing large logic traces, with the system having an input for regular expressions, a generator for receiving the regular expressions and generating finite automata which use arithmetic/logic expressions that permit the use of a substantially infinite alphabet, an input for a large trace array, and an analyzer for searching the large trace array with the finite automata, with the analyzer producing results of the search.

Abstract: A log for managing data in a shadow set of storage media includes a system for maintaining a log of address information associated with at least one write command received from one of a plurality of data processing devices. The system for maintaining a log of address information includes a device for receiving a write command from a data processing device, a device which writes data associated with the write command in a section of one of the storage media, and a device which writes address information in a log indicative of the location of that section. A device is provided which then implements a management operation on data stored on one of the storage media in accordance with the address information stored in the log.

Abstract: A video teleconferencing method and apparatus for computer workstations connected by a digital data network includes a transmission source portion for a local workstation to send audio and video teleconference data across the network to one or more remote workstations, and, a receiver for the local workstation to receive audio and video teleconference data back from the remote workstations. The local workstation sends teleconference data to each of the remote workstations over a variable bandwidth digital data connection, and each of the remote workstations returns teleconference data back to the local workstation over another variable bandwidth digital data connection. The transmission source portion includes a master software process executing on the local workstation, and the receiver includes a slave software process executing the remote workstation.

Abstract: The distributed computation of max-min fair rates in general require lookups for all connections. This present method includes a distributed process for computing max-min fair rates in response to a rate allocation request by any connection. The method computes the optimal rate by performing a single lookup of the state for a particular connection. The discrepancies due to omitting the lookup for other connections are corrected when those connections request a rate allocation.

Abstract: A self-timed logic device which produces internal control and timing signals in response to an external signal is described. The circuit includes means responsive to a pulse signal for providing control and timing signals and means responsive to a change in state of a signal fed to said device for providing said pulse signal. The means for providing said pulse further includes means for selectively changing timing characteristics of said device in response to external tuning signals fed to the device. In a preferred embodiment the logic device is a static random access memory.

Abstract: An arbiter of an I/O controller implements an arbitration process for controlling bi-directional data flow between a local area network and a main memory connected to a system bus having variable latency. A receive state machine of the controller manages inbound data bursts from the network by temporarily storing the data in a receive buffer before transfer to the main memory. Outbound data bursts from the main memory are managed by a transmit state machine of the controller, and are temporarily stored in a transmit buffer prior to transmission onto the network. The arbitration process assigns each of the receive and transmit state machines priority for accessing the system bus depending upon certain status conditions of the controller.

Abstract: This invention relates to an image processing system which relies upon quantization and dithering techniques to enable an output device, which has a given number of output levels, to accurately reproduce a image which is generated by an input device, which has a greater or equal number of input levels. Generally, neither the number of input nor output levels need to be a power of two. The present invention is implemented in a number of different embodiments. These embodiments generally rely upon an image processor which, depending on the particular implementation, includes memory devices and an adder, a comparator, or a bit shifter. Additional embodiments use an image adjustment system to refine the raw input levels of the input device, in order to create an improved output image. Also, the particular embodiments of the image processors can be used in connection with imaging systems having bi-tonal, monochromatic, or color input and output devices.

Abstract: An apparatus and method for caching SMRAM in an Intel.RTM. CPU employing system management mode. A cache for the CPU includes a plurality of data entries and an SMRAM status bit corresponding to each data entry. The SMRAM status bit is set if the data entry holds data in SMRAM, and reset if the data entry does not hold data in SMRAM. The SMRAM status bit distinguishes SMRAM data from system memory data in the cache, thereby eliminating cache coherency problems.

Abstract: A document management apparatus minimizes the busy time of a cursor by using asynchronous servicing of responses from repositories, and by executing the cursor control process during time intervals between receiving responses. Also during these time intervals, other processes can be launched in response to actions using the cursor and commands initiated by the user. The apparatus has a find tool to transmit a first search request for a category of documents; processing a first response to the first request, the first response having a list of documents found in the category; and transmitting a search request for selected attribute value pairs for each document in the list. The apparatus has a display comprising: a document display for displaying a blank document screen object for each document in the list; updating a screen object corresponding to a document whose attribute is received by the apparatus, the update occurring in response to receipt of a message carrying the attribute and corresponding value.