Abstract: Read-write buffer apparatus is provided for reducing the time necessary to resolve read conflicts during normal and block mode read requests. Additionally, the read-write buffer apparatus provides a means for gathering non-sequential write requests in an internal write buffer, thus reducing the frequency of a buffer full condition. The enhanced read-write buffer apparatus minimizes CPU wait states, while increasing the CPU processing rate and improves overall data processing system throughput.

Abstract: A system for controlling the transmission of cells from a network node over multiple Virtual Circuits (VCs) is disclosed. The system performs traffic shaping, as required by connection based systems such as Asynchronous Transfer Mode (ATM), for each VC connected with a network node, so that the Quality of Service (Qos) parameters established when the connection was established are not exceeded. The system includes a process for scheduling the transmission of cells from the network node. The scheduling process periodically scans a table having entries corresponding to virtual circuits connected with the network node. During each scan of the table, the scheduler increments a sustainable rate accumulator field, a peak rate accumulator field, and a latency accumulator field of each table entry that corresponds with a virtual circuit that is open, and for which there is a cell ready to be transmitted.

Abstract: A method for arbitrating conflicting requests for a memory transfer in a multiport memory system including first and second memory ports. The method includes the following steps. First, monitoring the volume of memory transfer requests from the first memory port. Second, partially disabling the second memory port if the memory request volume is greater than a first predetermined volume. And third, reenabling the second memory port when the memory request volume becomes less than a second predetermined volume. Apparatus implementing this method which includes an activity detector, coupled to the first memory port, for generating a bistate signal having a first state when the volume of memory requests by the first memory port exceeds a first predetermined volume and a second state otherwise. Circuits are provided for selectively partially disabling memory requests from the second memory port in response to the bistate signal being in the second state.

Abstract: An arrangement for selective filtering, e.g. one-way filtering, of messages received by a 2-port bridge from stations connected to two LANs of an extended LAN is provided. The bridge includes a message filtering database containing the addresses of all stations connected to one of the LANs. The database also contains a list of higher-level protocols employed by the stations. Associated with each protocol-type is information used by the bridge to dispose of the message. The message filtering database comprises a single table memory capable of supporting both ports of the bridge. The selective filtering process involves a two-step analysis by the bridge to determine whether to discard the message or forward it to another port. The analysis is based on a destination address and a protocol-type of the received message.

Abstract: A DRAM memory controller for a printer having a single host CPU and a bitmap memory. The CPU initiates data transfers synchronously to a system clock for filling the bitmap memory, and a DMA controller initiates data transfers asynchronously to the system clock for transferring data from the bitmap memory to a print engine. The controller includes a first sequencer for controlling synchronous data transfers initiated by the host CPU, a second sequencer for controlling asynchronous data transfers initiated by the DMA controller, a refresh request generator for generating a refresh request signal which is asynchronous to the system clock, and a third sequencer for controlling memory refresh and for controlling arbtitration betwween the first, second, and third sequencers. Also provided is a method of transferring data between a bitmap memory and a print fifo in a printer.

Abstract: A host system and an ATM network adapter using a chaser packet are presented. The adapter receives cells over a virtual connection on the network and generates, in response to the host system, a chaser packet which allows the host to detect that all data has been transferred form the adapter buffers to host memory. When all data has been transferred, the host may release the virtual connection without data loss. The host and adapter may also transmit data. In data transmission, the chaser packet is used to determine that all data has been transmitted out onto the network before the sending host releases the virtual connection. The chaser packet is also used for resynchronization of credits where the ATM network uses credit-based flow control. The adapter uses the chaser packet to drain the local queue so that the link between the adapter and a source system may be resynchronized.

Abstract: A multicast connection arrangement is provided by which a source node may establish multicast virtual circuits to a group of destination nodes of an arbitrary-topology network using a single procedure, and may subsequently modify those circuits, i.e., add or delete destination nodes, with a single, related procedure. The arrangement includes a multicast setup packet for opening the multicast virtual circuits, the packet containing a multicast identifier field, a virtual circuit field and a destination field identifying a list of desired destination node addresses. The multicast setup packet may be also used to add destination nodes to the circuits while a multicast delete packet is used to delete nodes from the circuits. When adding nodes to the multicast virtual circuits, a topology analysis process is provided to prevent the formation of an unstable network topology.

Abstract: This invention relates to an image processing system which relies upon quantization and dithering techniques to enable an output device, which has a given number of output levels, to accurately reproduce a image which is generated by an input device, which has a greater or equal number of input levels. Generally, neither the number of input nor output levels need to be a power of two. The present invention is implemented in a number of different embodiments. These embodiments generally rely upon an image processor which, depending on the particular implementation, includes memory devices and an adder, a comparator, or a bit shifter. Additional embodiments use an image adjustment system to refine the raw input levels of the input device, in order to create an improved output image. Also, the particular embodiments of the image processors can be used in connection with imaging systems having bi-tonal, monochromatic, or color input and output devices.

Abstract: A plurality of indexes are provided for a multi-way set-associate cache of a computer system. The cache is organized as a plurality of blocks for storing data which are a copies of main memory data. Each block has an associated tag for uniquely identifying the block. The blocks and the tags are addressed by indexes. The indexes are generated by a Boolean hashing function which converts a memory address to cache indexes by combining the bits of the memory address using an exclusive OR function. Different combination of bits are used to generate a plurality of different indexes to address the tags and the associated blocks to transfer data between the cache and the central processing unit of the computer system.

Abstract: An interconnect structure formed of a flexible, multilayer dielectric material such as polyimide, having a support ring, connection points on the section inside the support ring for connecting one or more semiconductor chips, and connection points outside the support ring for connecting to a circuit board. Alignment templates are disclosed which align the semiconductor chip with the connection points.

Abstract: A method and apparatus for virtual data integration in a database management system, specifically for providing multidatabase query and retrieval capability, where queries are generated at a user interface and passed to one of a plurality of databases. An organization engine (OE) is coupled to the user interface and, via an organization engine/database interface for each database, to the databases. The organization engine comprises a software module that passes a MakeCallBack routine along with the user query to the OE/database interface. The query is passed on to the database. If the queried data is not found at the queried database, but rather a reference to another database is found there, then that reference is passed back with a CallBack routine to the OE. The query is then redirected to the referenced database, and repeats the procedure until the sought data is actually located.

Abstract: A method of scheduling processes on a symmetric multiprocessing system that maintains process-to-CPU affinity without introducing excessive idle time is disclosed. When a new process is assigned, the process is identified as young and small, given a migtick value and assigned to a specific CPU. If the priority of a process placed on a run queue is above a threshold, the high priority count of the assigned CPU is incremented. At predetermined clock intervals, an interrupt occurs that causes the migtick value of running processes to be decremented. Then each CPU is tested to determine if its high priority count is greater than zero. CPUs having high priority counts greater than zero are tested to determine if any processes having a priority greater than the priority of the running process are assigned. If higher priority processes are assigned to a CPU having assigned processes lying above the threshold, a context switch takes place that results in the higher priority process being run.

Abstract: Disclosed is a position independent code system that enables a programmable digital data processing system to invoke and execute procedures and access data that are loaded into system memory at addresses that are not specified by the program code and are not determined until the program code is compiled, linked and loaded into system memory. The coded call sequence instructions that are provided by the disclosed position independent code allow a procedure to call another procedure and are based upon the value that is stored in a dedicated register (or equivalent memory space) of the system and memory offset pointers, which are determined during system compilation and linking of program code and which indicate the memory location of the calling procedure and the call sequence of the calling procedure relative to the memory location at which the system stores the address of the procedure being called. When a call sequence is executed, the address of the called procedure is transferred to the dedicated register.

Abstract: Global serializability in a distributed computing system having a plurality of resource managers is guaranteed by selectively committing global transactions, and aborting or delaying commitment of transactions to enforce an order of commitment of global transactions that is the same as an order of conflicts among the global transactions, including indirect conflicts caused by local transactions. These conflicts are detected, for example, by maintaining a serializability graph in each resource manager recording the effects of local as well as global transactions, including the effects of committed local transactions. The serializability graph includes nodes representing transactions, directed edges representing direct conflicts, and paths including more than one edge representing indirect conflicts. By referencing the serializability graph, global serializability is achieved in a most efficient manner.

Abstract: A data storage system using a RAID array and a logging process and apparatus that identifies a parity block that may not contain the proper parity for its associated data blocks and which prevents such inconsistent parity information from being used in the regeneration of unavailable data. A small fraction of the blocks of each disk are dedicated to storing parity metadata bits. The parity metadata is associated with the parity blocks and identifies whether or not each parity block contains the proper parity information for its associated data blocks or may contain invalid information. The data integrity of the RAID array is preserved by preventing the generation of undetected corrupt data.

Abstract: Serializability across distributed transactions is guaranteed by selectively committing and aborting or delaying transactions to enforce an order of commitment that is the same as an order of performance of conflicting component operations of the transactions. A first memory access operation in a first transaction, for example, conflicts with a second memory access operation in a second transaction when the two memory access operations reference the same memory location and at least one of the operations is a write operation. The transaction processing system may permit a second transaction to read data written by a write operation of a first transaction before the first transaction is committed. In this case, depending on the respective order in which the two conflicting operations occur, the order of commitment is enforced, possibly by aborting either of the two transactions, to ensure that the order of commitment is the same as the order of the operations.

Abstract: The problems of efficiently building a large software system are solved by the present invention of language scoping for effective configuration descriptions. A software system is defined by a tree of system models which are written in a functional language. The functional language provides a unique combination of static and dynamic scoping. This combination is required to write modular, flexible, and concise, yet complete, configuration descriptions.

Abstract: An apparatus for forwarding a data packet from a first link to a second link is disclosed. The apparatus is coupled with a plurality of computer networks through ports on the apparatus. The apparatus maintains a spanning tree list indicating which of the apparatus ports are active. The apparatus receives a packet, and determines if the packet was received from a port that is active. If the packet was received from a port that is not active, the packet is discarded. If the packet is not discarded, the data link source address of the packet is stored in a database within the apparatus for the computer network coupled with the port from which the packet was received. The apparatus then decides, responsive to a contents of a data link destination address field in the packet, whether to forward the packet as a bridge or to forward the packet as a router.

Abstract: A method of specifying the operands for a microcoded CPU employs a combination of a set of microinstruction routines for generic operand modes, along with hardware primitives for selecting various specific types of operand treatment. Decoding of a machine-level instruction produces an entry point for the microstore, selecting one of the set of generic operand modes. Also, decoding of the instruction produces control bits that are used directly to select the specific operand type or used by the hardware primitives. In this way, branching is avoided in the microinstruction sequences used for operand specifying, but yet the amount of microcode needed is a minimum.

Abstract: A distributed computation system has a set of agents that perform each specified distributed computation. State transition events in each agent are conditioned or dependent on state transition events in other ones of the agents participating in the same distributed computation. The event dependencies between events in the agents are dynamically specified at run time from a set of predefined dependency types. The assigned conditions for resolving the truth value of these events are stored in local knowledge databases in each of the agents. Each agent stores in its local knowledge database a representation of the conditions for local events, which are state transition events in that agent, and a representation of the conditions for those external events that depend on notifications of local events in this agent and for those external events on which the local events are dependent. The local knowledge database also stores status information on the current truth value of the local and external events.