Abstract: An I/O bus interface cell includes a driver circuit having an input terminal fed by a logic signal and an output terminal to produce in response thereto a drive signal having selectable rise and fall time characteristics in accordance with a reference voltage provided to the driver. The I/O cell also includes a receiver circuit having an input terminal coupled to said output terminal of said driver with the receiver disposed to latch an unresolved, unamplified received signal prior to resolving the state of the signal. The I/O cell further includes a termination circuit having a terminal connected to the output of said driver, and having a selectable impedance characteristic at said terminal, with said selectable impedance being in accordance with a reference voltage provided to an input of said termination circuit. Preferably, the I/O cell the driver, receiver and termination circuits are fabricated on a common semiconductor substrate.

Abstract: The invention method and apparatus employs font metrics data related to font bitmaps for characters of a desired font. Position offsets of pieces in composite characters are read from the font metrics data and are converted to the appropriate pixel offset to adjust the bitmaps of subject compressed font characters. The adjusted bitmaps of the different pieces of a subject composite character are combined to form a working bitmap which represents each piece of the composite character in full size in the subject font. Screen display of composite characters decompressed to full-size is supported by the formed working bitmaps.

Abstract: A method and apparatus for aliasing an address for a location in a memory system. The aliasing permits an address generating unit to access a memory block of variable size based upon an address space of fixed size so that the size of the memory block can be changed without changing the address generating software of the address generating unit. The invention provides an address aliasing device arranged to receive an address from the address generating unit. The address aliasing device includes a register that stores memory block size information. The memory block size information is read by the address aliasing device and decoded to provide bit information representative of the size of the memory block. The address aliasing device logically combines the bit information with appropriate corresponding bits of the input address to provide an alias address that is consistent with the size of the memory block.

Abstract: A processor and method for delaying the processing of cache coherency transactions during outstanding cache fills in a multi-processor system using a shared memory. A first processor fetches data having a specified address by addressing a cache memory, and when the specified address is not in the cache, saving the specified address in a fill address memory, and sending a fill request to the shared memory. Before return of fill data, the first processor receives a cache coherency request including the specified address from a second processor requesting invalidation of an addressed block of data. The first processor responds by checking whether the fill address memory includes the specified address, and upon finding the specified address in the fill address memory, delaying execution of the cache coherency request until the fill data is returned, and when the fill data is returned, using the fill data without retaining a validated block of the fill data in the cache.

Abstract: A novel method and apparatus for managing user requests throughout a distributed processing system permits the tracking and managing of a request as it propagates throughout a transaction processing (TP) system; and provides a method and mechanism for communication between an end-user client and any server working as a result of the end-user client's initial request.

Abstract: A processor and method for preventing access to a locked memory block in a multiprocessor computer system. The processor has a cache memory and records a memory lock in a content-addressable memory separate from the cache memory. Preferably, outstanding cache fills are recorded in the same content addressable memory as memory locks, and a memory lock or an outstanding cache fill delays the execution of a cache coherency request upon the same memory block. When a cache coherency request is received from another processor, the address of the cache coherency request is compared to addresses stored in the content addressable memory, and when there is a match, a bit in the matching entry is set to indicate a delayed request that is executed after the lock is unlocked or the cache is refilled. In a specific embodiment, a memory lock or an outstanding cache fill also stalls a processor read or write to the same memory block.

Abstract: Methods and apparatus for verifying--in a network comprised of LANs and bridges connected to LANs, in which the bridges associate the LANs with LAN numbers--that bridges connected to a given LAN have been configured with the same LAN number for that LAN. A first bridge encodes the LAN number configured for the given LAN into a LAN number verification message and transmits the message to a second bridge connected to the LAN. The second bridge then compares the LAN number encoded in the received LAN number verification message to the LAN number configured for the LAN at the second bridge. A bridge which performs this method includes storage for associating the LANs connected to the bridge with LAN numbers, an encoder for encoding the LAN number for a given LAN into a LAN number verification message, and a transmitter for transmitting the LAN number verification message onto the given LAN.

Abstract: A Faraday shield minimizes the leakage of electromagnetic interference (EMI) and radio frequency interference (RFI) of a maximum frequency and corresponding wavelength that emanates from electronic components contained within the shield. The top and bottom each contain apertures that are dimensioned to effectively block the escape of EMI and RFI from the shield and to permit the flow of air to dissipate heat without generating acoustic noise. The thickness of the top of the shield is at least one half of the diagonal length across the largest of the apertures located in the top. The length of the longest aperture side is less than one fourth of the wavelength of the maximum frequency of EMI and RFI contained by the shield. Corresponding relationships exist between the apertures located in the shield bottom and its thickness.

Abstract: Loop-back detection and signalling is achieved on any DS-0 channel that conforms to 56 kbps operation such as DDS in a DS-1 digital data transmission system. A standard DS-1 chip set (line interface unit, framer, and link layer controller) is used, coupled to 24 transmit and receive buffer means in the customer main memory. The framer detects control bits by using Channel Associate Signalling, (designed for digitising voice in-band signalling and not normally used for data transmission), in the incoming signal and interrupts the customer CPU, which determines from the framer which channel caused the interrupt, changes the mode of the relevant channel, checks that channel's receive buffer means for loop-back codes, and, if enough successive loop-back codes are found, copies the receive buffer means into the transmit buffer means (with code mapping) for as long as the loop-back condition exists.

Abstract: A pedestal assembly having two opposing and abutting parts, each including a base portion, a wall, both a locking extension and a locking recess, such that the two parts interlock to create a floor region for holding a computer enclosure.

Abstract: Methods and apparatus for automatically assigning LAN numbers to LANs in a network comprised of LANs and bridges connected to LANs. The bridges associate the LANs with LAN numbers and each LAN is related to one of the bridges. A central database links each LAN (identified by LAN number) to the identity of its related bridge and the port of that bridge which is connected to the LAN. To obtain a LAN number for a given LAN, the bridge related to the given LAN transmits a request identifying the related bridge and the port of the related bridge which is connected to the given LAN. In response, a LAN number which has not been associated with any LAN other than the given LAN is selected and included in a response which is sent back to the requesting bridge. The requesting bridge then transmits LAN number identification messages incorporating the selected LAN number to the other bridges on the given LAN.

Abstract: This invention allows each of a plurality of windows to use its own distinct datatype and format while more than one window is being displayed on a monitor screen of a computer video graphics system. Different windows can use full color or pseudocolor frame buffer organizations, can use overlay planes or not, and can have other differences in the interpretation of the pixel values without affecting each other. Window dependent pixel datatypes are provided by means of a lookup table that is contained in logic between the frame buffer and the colormap/DAC that drives the monitor. This lookup table contains descriptors for pixel datatypes. It is indexed by a window number that is specified for each pixel. The pixel datatype descriptor accessed at each pixel is then used to control logic that processes that pixel value to create an index for the colormap. This allows each window to specify its own pixel datatype and format, that is used to interpret the pixels contained in the window.

Abstract: Input values are data encoded for improved signal characteristics (e.g., limited maximum run length and limited cumulative DC-offset) so as to form "data codewords," and then a number of the data codewords, collectively referred to as a block, are error protection encoded, preferably using a conventional linear and systematic forward error control ("FEC") code, to yield an FEC code block. Preferably, an FEC code block is formed by generating a number of check bits or FEC bits equal to the number of data codewords in the block, and then concatenating one FEC bit and its binary complement with each data codeword, so that one FEC bit and its complement is interposed between each successive codeword.

Abstract: A pipelined CPU executes instructions of variable length, and references memory using various data widths. Macroinstruction pipelining is employed (instead of microinstruction pipelining), with queueing between units of the CPU to allow flexibility in instruction execution times. A branch prediction method employs a branch history table which records the taken vs. not-taken history of branch opcodes recently used, and uses an empirical aglorithm to predict which way the next occurrence of this branch will go, based upon the history table. The branch history table stores in each entry a number of bits for each branch address, each bits indicating "taken" or "not-taken" for one occurrence of the branch. The table is indexed by branch address. A register stores the empirical aglorithm, and upon occurrence of a branch its history is fetched from the table and used to select a location in the register containing a prediction for this particular pattern of branch history.

Abstract: A method for generating test programs for an implementation of a specification that has been modeled as an extended finite state machine (EFSM), the EFSM including vertices and transitions, where the transitions represent functions to be performed by the implementation, including predicates and actions such as variable assignments. The method includes traversing the EFSM in a depth-first manner from a root model start state to a root model exit state, through intermediate vertices which may be normal states or models. Models include further vertices and transitions, and may be called as submodels or as go-to models, where a go-to model includes an EFSM exit state. The EFSM may be traversed exhaustively, such that all possible paths are traversed, or in a partial transition coverage mode, where a user-defined subset of the possible paths are traversed.

Abstract: An arrangement for a token ring communications network includes nodes for transmitting and receiving data signals. Also provided is a communications medium for transporting the data signals includes a trunk circuit having a plurality of trunk segments, each trunk segment having an input end and an output end and a plurality of lobe circuits for connecting the nodes to the trunk circuit. A plurality of wiring concentrator are provided for connecting adjacent trunk segments as a ring. Each wiring concentrator having a plurality of ports including an input port connected to an input end of one of the trunk segments, an output port connected to an output end of one of the trunk segments, and a lobe port connected to one of the lobe circuits. Each wiring concentrator includes an internal trunk, a controller, and a plurality of switches for interconnecting the ports while the voltage and the frequency of the data signal are within predetermined voltage and frequency ranges.

Abstract: The invention is a compression method which provides the advantages of run-length compression while preserving the natural collating order of the data. The method of the invention replaces sequential repetitions of a target pattern beyond a threshold value followed by a single number which encodes both the repetition count and the collating relationship between the target pattern and the pattern which follows it in the uncollated sequence. In the preferred embodiment of the invention, the code is preceded by at least one repetition of the pattern. In the preferred embodiment of the invention, the numerical code is set as the difference between the run count and the threshold count if the following pattern is less than the target pattern, or if there is no following pattern. If the following pattern is greater than the compression sequence, the code is set as a predetermined number, preferably the maximum binary value of the sequence length, minus the difference between the run count and the threshold count.

Abstract: This disclosure describes an Interconnect Stress Testing (IST) system and a printed wiring board test coupon which is used with the IST system. The system includes a computer device and a cabinet which is used for mounting the test coupon as well as housing a number of the other components that make up the system. During a pre-cycling phase, the system determines the correct current that should be passed through the coupon in order to heat it to a predetermined temperature. After that test current value is determined the system actually stress tests the coupon by passing the determined test current through the coupon. It does so for a selected number of cycles, and monitors resistance changes in the coupon during testing while recording test data. This disclosure also describes the test coupon, which is designed to uniformly dissipate the heat created during stress cycling.

Abstract: Information needed by application programs from a secondary storage is cached in a cache memory which is organized in multiple levels, each level having multiple entries, the entries of each level receiving information of a predetermined category, each entry being accessible independently. Links are defined between entries of one level of the cache memory and entries at another level of the cache memory, the links corresponding to information relationships specified by a user of information stored in the secondary storage. In response to a request to a file system from an application for needed information, the needed information is fetched into the cache, and in connection with fetching the needed information, other information is prefetched from the system of files which is not immediately needed. Quotas are established on information which may be fetched from a secondary storage into the cache, the quotas being applicable to file contents within a file and to the number of files within a directory.

Abstract: A packet data communication network employs a local switch, router or bridge device functioning to transfer packets between segments of a larger network. When packets enter this device, an address translation is performed to generate local source and destination addresses which are much shorter than the globally-unique addresses contained in the packet as dictated by the protocol. These local addresses are inserted in a header that is added to the packet, in addition to any header already contained in the packet. This added header travels with the packet through the local switch, router or bridge device, but then is stripped off before the packet is sent out onto another network segment. The added header may also contain other information, such as a local name for the source and destination segment (link), as well as status information that is locally useful, but not part of the packet protocol and not necessary for transmission with the packet throughout the network.