Abstract: A telecommunications network of the type having links with long propagation delay uses an asynchronous transfer mode in which small, fixed-length blocks of information (cells) are transferred at very high speed. Each long-haul hop within the network is phase-locked to a fixed period, and time slots of a granularity of one cell are pre-allocated to the virtual circuits. The network operates in a near-synchronous (plesiochronous) manner. By pre-allocating cells, it is assured that the cells will not arrive at a faster rate than that at which each receiving node can forward them on to the next hop. When bursts of heavy traffic occur, the network responds by slowing or limiting access, rather than by loss of data at intermediate nodes due to buffer overflow.

Abstract: An application event collector which is embodied in computer software that collects event-based data. The collector follows a process which includes the steps of: (a) storing definitions of event-marking instructions that have been embedded in the software application, each instruction being capable, when enabled, of collecting event-based data, and the definitions identifying the software application in which the instructions have been embedded and the type of data collected by the instructions; (b) selecting, prior to or during execution of the application, a subset of the event-marking instructions and enabling those instructions; and (c) detecting the enabled event-marking instructions, during execution of the software application, and collecting the data specified by the enabled instructions. The application is divided into layers, each of which may have event-marking instructions embedded in it.

Abstract: A distributed computer system includes a multiplicity of concurrently active processes. Each object is owned by one process. Objects are accessible to processes other than the object's owner. Each process, when it receives a handle to an object owned by any other process, sends a first "dirty" message to the object's owner indicating that the object is in use. When a process permanently ceases use of an object handle, it sends a second "clean" message to the object's owner indicating that the object is no longer in use. Each object's owner receives the first and second messages concerning usage of that object, stores data for keeping track of which other processes have a handle to that object and sends acknowledgement messages in return. The receiver of an object handle does not use the handle until its first message is acknowledged.

Abstract: A method and system for compiling a source program using smart recompilation. The invention allows fragments to contain "invocation specific" information, which is generated during a code generation phase of compilation. A hint generator attempts to preserve values of the invocation specific information between successive invocations of the compiler.

Abstract: A fixture (10) for bonding multiple components together includes a bottom plate (20), a middle plate (22) and a top plate (24). The plates (20), (22) and (24) are aligned by dowels (26) and clamps (30). Bottom plate (20) has a rectangular pocket (32) for holding heat sink (14) and alignment pins (34) for locating plastic pin grid array (PPGA) package (12) over the heat sink (14). An annular projection (40 ) covered with a conformal pad (42) extends from bottom surface (44) of the middle plate (22). Dowel (50) extends through openings (46) and (36) in the top and middle plates (24) and (22) to apply pressure to chip (16). A first spring (56) is mounted on the dowel (50) and compressed between the top plate (24) and a snap ring (58) to provide pressure from the dowel (50 ) on the chip (16). A second, larger diameter spring (60) is compressed between the middle plate (22) and the top plate (24) to provide pressure from the middle plate (22) on the PPGA (12).

Abstract: A method of testing an integrated circuit having a plurality of pins includes the steps of providing a functional test set having an ordered group of test strings wherein each element of the test string is related to one of the pins of said integrated circuit. The group of test strings is searched to locate a sequence of test strings having a undesirable pattern. The undesirable pattern can be a pattern in which none of the elements associated with the test string changes or a pattern in which a reference element and at least one other element of the test string changes. When a sequence of test strings having the undesirable pattern is located, the group of test strings is processed to correct the undesirable pattern. When all the vector sequences having an undesirable patterns are corrected, the group of test vectors is applied to the input pins of the integrated circuit.

Abstract: A computer system using virtual memory addressing and having a direct-mapped cache is operated in a manner to simulate the effect of a set associative cache by detecting cache misses and remapping pages in the main memory so that memory references which would have caused thrashing can instead coexist in the cache. Two memory addresses which are in different pages but which map to the same location in the cache may not reside in the direct-mapped cache at the same time, so alternate reference to these addresses by a task executing on the CPU would cause thrashing. However, if the location of one of these addresses in main memory is changed, the data items having these addresses can coexist in the cache, and performance will be markedly improved because thrashing will no longer result. For a CPU executing a virtual memory operating system, a page of data or instructions can be moved to a different physical page frame but remain the same virtual address.

Abstract: In a system for interactively viewing videos, a selected video is transmitted as a plurality of frames of digitized video data for playback on a viewing device. The system receives the transmitted video data and includes a memory buffer for storing a segment of a selected one of the videos. The segment includes a predetermined number of frames representing a predetermined time interval of the selected video. In addition, the memory buffer including a write pointer and a read pointer. Software controlled servers are provided for witting and reading video data of the selected video to and from the memory buffer, independently, at locations indicated by the write and read pointers to transfer the selected video to the viewing device. By using a remote controller the viewer can position the read and write pointers to view any portion of the selected video interactively.

Abstract: A content addressable memory, utilizing address recognition mechanism, comprising a Random Access Memory (RAM) including a plurality of data storage locations. Each of the data storage locations has a unique address. The content addressable memory operates to store a data entry comprising predetermined match information for at least a portion of a data entity. Each at least a portion of a data entity comprises the unique address of the respective data storage location. The RAM has an address port for input of at least a portion of a data entity as an address and an output for outputting the stored data entries. The RAM operates to fetch the data entry stored at the input address and to output the stored match information corresponding to the at least a portion of a data entity, in response to input of the at least a portion of a data entity as an address to the RAM. In a particular embodiment, the RAM comprises an array of n RAMs, wherein the at least a portion of a data entity is segmented into n slices.

Abstract: Prior to sorting, the amount of data in each record of a collection of records is normalized to a value chosen from a designated set of values. The designated set of values selected from a progression of numbers computed as an integer power of two. The normalized collection is partitioned into a plurality of sub-sets of records to be sorted in parallel. Sorted sub-sets of records are merged to arrange the records in a predetermined order.

Abstract: In distributed heterogeneous data processing networks, dispatcher and control server software components execute the code of a single application or of many portions of the code of one or more applications in response to a method object received from a client application. The method object includes a reference to the code to be executed.

Abstract: A network adapter with an interrupt generation circuit to minimize the number of host computer system interrupts needed to notify the host computer system that the network adapter has consumed one or more host memory buffers. The interrupt generation circuit issues an interrupt to the host computer system when the host computer system has entered both a transmit sleep state and a receive sleep state, and the network adapter has consumed a host memory buffer not processed by the host computer system. When the host computer system has no work to do with respect to transmit buffers in the host computer memory, it enters a transmit sleep state and indicates to the network adapter the last transmit buffer it processed. When the host computer system has no work to do with respect to receive buffers in the host computer memory, it enters a receive sleep state and indicates to the network adapter the last receive buffer it processed.

Abstract: A technique for managing bidirectional data flow between a first data bus, such as in a local area network, having a fixed data flow rate once access has been obtained, and a memory or storage device connected to a second data bus having variable latency. Inbound data from the first data bus are temporarily stored in a receive buffer memory and later forwarded to the storage device. Outbound data bursts are retrieved from the same storage device, temporarily stored in a transmit buffer memory, and later transmitted onto the first data bus. The invention controls the steps of forwarding inbound data to the storage device and retrieving outbound data from the storage device, in such a manner as to make efficient use of the second data bus and to minimize the possibility of overflowing the receive buffer memory during a receive operation, or underflowing the transmit buffer memory during a transmit operation.

Abstract: A distributed computer system employs a license management system to account for software product usage. A management policy having a variety of alternative styles and contexts is provided. Each licensed product upon start-up makes a call to a license server to check on whether usage is permitted, and the license server checks a database of the licenses, called product use authorizations, that it administers. If the particular use requested is permitted, a grant is returned to the requesting user node. The product use authorization is structured to define a license management policy allowing a variety of license alternatives by values called "style", "context", "duration" and "usage requirements determination method". The license administration may be delegated by the license server to a subsection of the organization, by creating another license management facility duplicating the main facility.

Abstract: A technique for modifying the IEEE 802.3 standard for selecting backoff times in a Carrier Sense Multiple Access with Collision Detection (CSMA/CD) network, in the event that a collision is sensed by a node that has captured the network communication channel. If there is a small number of active nodes on the network, one node may capture the channel and the standard backoff algorithm makes it increasingly unlikely for another node to transmit. The new technique provides for less aggressive, i.e. longer, backoff times before at least the first retransmission attempt made by a node that has captured the channel, and in addition provides for the use of a stopped backoff algorithm. Three specific examples of methods to choose a backoff time and two methods of using a stopped backoff algorithm are disclosed.

Abstract: A circuit board is ejected from an electrical chassis by inserting a pair of implements into corresponding pairs of apertures disposed on opposing side members of the electrical chassis. The end portions of the implements are engaged in a first pair of notches, each one being disposed on each of a pair of opposing edges of the circuit board provided within the electrical chassis, and a force is exerted on each of the first notches disposed on each of the pair of opposing edges of the circuit board with the pair of implements, to disengage the circuit board from a connector located at one end of the electrical chassis.

Abstract: A method for connecting a first communications system with a second communications system is disclosed. A first frame is received at a first station. The first station is connected to both the first communication system and the second communication system. The first frame has a destination address field, and the destination address field contains a desired destination address. The first station forwards, in response to the desired destination address, the first frame onto the second communications system as a second frame, and the first station writes a second destination address into a destination address field of the second frame. The first station writes the desired destination address into a predetermined field of the second frame. The first station writes, an indicator into the second frame, the indicator is capable of being interpreted by a receiving station to mean that the desired destination address is written into the predetermined field of the second frame.

Abstract: A novel mechanism prevents interleaving of packet cells from different source nodes on the same multicast port group at switches of a multicast virtual circuit in a cell-switched network: however, different cells bound for different multicast port groups may be interleaved. The mechanism comprises specific routing information that is stored in each multicast group port entry of a forwarding table located within each switch of the multicast virtual circuit. The forwarding table also stores information relating to each multicast port group including a virtual circuit value for each port of the multicast group. The specific routing information is provided for each multicast port group entry to notify the switch when data traffic for a particular packet is pending through a port of the multicast group and when that data traffic ceases, i.e., when the "end-of-packet" is reached. This ensures that the packets may be correctly reassembled at the destination nodes.

Abstract: A method and apparatus for controlling memory access operations of a pipelined processor using a "write queue" are described. The write queue temporarily stores addresses of writes not yet made in memory. Each write queue entry includes a write-read conflict bit. When an entry is first put into the write queue, the write-read conflict bit is cleared. When a subsequent memory read request occurs, the address of the read request is compared to the addresses stored in the write queue. If there is a match, the write-read conflict bit in the matching entry is set. If after this comparison no conflict bits are set, the read is allowed to proceed to memory before the queued writes. On the other hand, if any conflict bits are set, the read is prevented from proceeding. The conflict bits are cleared as the queued writes are performed in memory. Also, the write queue is able to accept additional entries while a read request is stalled.

Abstract: A cache memory is divided into at least two collections of data which effectively provide higher and lower priority regions for retaining data within the cache. The cache is arranged to divide its stored data into a high-priority (protected) collection of data and a low-priority (probationary) collection of data. Each collection of data is organized as a list, with a most recently used (MRU) end and a least recently used (LRU) end. Data accessed from either of the collections is added to the MRU end of the protected collection, having been removed from its previous place in either of the lists of collections. Data in any of the collections which is least recently used is removed from that collection as space is needed for other data. Newly acquired data, such as retrieved from or written to a mass storage device such as a disk drive is added to the MRU end of the probationary collection. Data which is removed from the protected collection is also added to the MRU end of the probationary collection.