Abstract: A conductive, light-absorbing baseplate for use in a field emission display is disclosed. The interior surface of the baseplate is coated with a praseodymium-manganese oxide layer having a resistivity that does not exceed 1.times.10.sup.5 .OMEGA..multidot.cm. A field emission display is also disclosed which comprises the conductive, light-absorbing baseplate, as well as processes for manufacturing the baseplate, field emission display and the conductive, light-absorbing praseodymium-manganese oxide material used to coat the baseplate.

Abstract: A method for forming an electrical connection between a semiconductor die and a corresponding electrical component mounted within an electrical device is provided. The method includes wire bonding metal wires to the bond pads of the die and then severing the metal wires to form loose leads attached to the bond pads. With the die mounted to the electrical device, the loose leads are bonded to the electrical component using a bonding tip. In an illustrative embodiment, the electrical device is a field emission display package and the electrical component is conductive traces for the package. Advantageous, the method can be used to form the electrical connection between the die mounted in a sealed space and the corresponding electrical component which is outside of the sealed space.

Abstract: A reduced size field emission display eliminates selected horizontal lines to reduce the size of an array of emitter sets. In one embodiment, every Nth output of a row pointer is left disconnected such that for every Nth line of image, no row of the array is activated. The overall number of rows of the array can be reduced by the number of unconnected outputs of the row pointer. In another approach, every Nth pulse of a row clock is blocked by a clock dropping circuit. Because the row pointer does not receive the Nth pulse, the row pointer remains at a current row for the two scans of the column data. The (N-1)th row is thus overwritten.

Abstract: There is disclosed a luminescent phosphor having an average particle size of less than about 3 microns, as well as a bright luminescent phosphor having an average particle size of less than 5 microns and a luminescence of about 10-12 au. The bright luminescent phosphor is made by combing a yttrium or gadolinium host material with a europium dopant in a liquid to form a slurry, and then pulverizing the slurry to less than about 3 microns in average particle size. The pulverized slurry is then heated to yield the bright luminescent phosphor. The bright luminescent phosphor is particularly suited for use in high resolution display screens, and in screens which require low power consumption, such as laptop computers.

Abstract: Cold cathode passive matrix FEDs are fabricated by depositing a resistive layer on a substrate, and coated with a protective layer in which at least one hole is formed. Cathode material is deposited on the protective layer making direct contact with the resistive layer through the hole to form bases for the emitter tips which are subsequently etched from the cathode layer. The protective layer allows overetching of the cathode material to prevent tip-to-tip electrical shorts without attacking the underlying resistive layer.

Abstract: A field emission display includes an emitter driving circuit for providing current to emitters in the display. The emitter driving circuit includes a current mirror to monitor actual current to each pixel in the array. The actual current is then compared to a reference current derived from an image signal based upon an expected current draw of the emitter to produce an error signal. The error signal is fed back to the input of the emitter driver circuit and the emitter driver circuit produces a corrected emitter current in response. During transitions in the image signal, error detection is briefly disabled to allow the emitter driver circuit to respond to the image signal.

Abstract: In a field emission display, a microchannel plate is mounted between an emitter panel and a display screen. The inner walls of the cylindrical passageways through the microchannel plate are coated with a conductive layer which is connected to a plate voltage. Electrons emitted from the emitter panel travel through cylindrical passageways in the microchannel plate toward the display screen. As electrons pass through the microchannels, the electrons are multiplied and collimated to increase the intensity of the light emitted from the screen and to reduce the pixel size.

Abstract: An electroluminescent device is provided incorporating an emissive layer comprising a processible polymer matrix such as poly(methylmethacrylate) and a chromophoric component such as an asymmetric stilbene or distyrylbenzene. The chromophoric component is blended with the polymer matrix or covalently attached thereto as a side chain and is selected to emit radiation in the region 400 nm to 500 nm when excited to luminesce.

Abstract: The disclosure describes a method of attaching and electrically connecting first and second planar substrates, wherein the first and second substrates have inwardly-facing surfaces with matching patterns of bond pads. The method includes adjusting a wire bonder's tear. length to a setting which leaves a projecting tail of severed bond wire at a terminating wedge bond connection. Further steps include making a wedge bond to an individual bond pad of the first planar substrate with bond wire from the wire bender, and then severing the bond wire adjacent said wedge bond. The adjusted tear length of the wire bender results in a tail of severed bond wire which projects from said wedge bond and said individual bond pad. Subsequent steps include positioning the first and second planar substrates with their inwardly-facing surfaces facing each other, aligning the matching bond pad patterns of the first and second planar substrates, and pressing the first and second planar substrates against each other.

Abstract: The present invention develops several methods used in a semiconductor fabrication process to form a resistive material having a specific resistive value. A first method uses the steps of: forming a titanium layer over a silicon substrate; and subjecting the titanium layer to a rapid thermal processing cycle. A second method uses the steps of: forming a titanium layer over a silicon substrate; subjecting the titanium layer to a rapid thermal processing cycle; and forming a titanium nitride layer over the thermally processed titanium. A third method uses the steps of: forming an insulating layer over a silicon substrate; forming an undoped polysilicon layer over the insulating layer; forming a titanium layer over the polysilicon layer; subjecting the titanium layer to a rapid thermal processing cycle; and forming a titanium nitride layer over the thermally processed titanium. Additionally, the resistive structure can be capped using a nitride layer.

Abstract: A display rack for supporting and displaying articles, includes a plurality of elongate channels, each channel being of integral, one-piece, unitary construction formed in a single plastic molding operation. Each channel defines a pair of laterally spaced upstanding sidewalls, a substantially planar track connecting the sidewalls at the bottoms thereof, and a front member spaced above the track and connecting the sidewalls. The bottom of the front member, the front of the track, and the front of the sidewalls cooperatively define an aperture through which a substantial portion of a lead article in the channel may be viewed. The channels are secured in side-by-side, longitudinally parallel and transversely adjacent relationship. Preferably, the front of the track is devoid of any transversely extending upstanding lip or wall.

Abstract: A Field Emission Display ("FED") is disclosed having a brightness to project images. To achieve this benefit, the FED comprises a pixelator is coupled to a display for displaying and projecting the image. By design, the pixelator conducts a current, corresponding to a degree of brightness in the resulting panel display, through the display grid. A first resistor having a first value, is coupled between the pixelator and a voltage node or ground. Moreover, a second resistor having a second value comprising at most one half of the first value is employed. A switch for connecting the first resistor in parallel with the second resistor is utilized such that when a control signal is received, the switch is enabled and the equivalent resistance between the pixelator and a voltage node or ground is substantially reduced.

Abstract: This invention is a space-efficient pixel control circuit for a field emission flat panel matrix-addressable array display. The invention reduces by one the number of transistors required at the intersection of each row line and column line within the array. In addition, only two lines need be routed through the array (i.e., row and column). The array space saved by increased layout efficiency may be used to increase pixel density within the array. The new space-efficient pixel control circuit has a single transistor in a base electrode grounding path that is directly controlled by a row line. A current-limiting resistor is interposed between the single grounding transistor and a column line to which an inverse video signal is applied. The magnitude of the current through the current-limiting resistor is inversely proportional to the inverse column signal voltage. Thus, pixel brightness is directly proportional to the voltage drop across the current-limiting resistor.

Abstract: A process for separating FED baseplates or other types of die assemblies from one another without producing any particulate matter or slag that could damage some of the baseplates. In one embodiment a high energy beam is aligned with a cutting line on the wafer that defines a path between the die assemblies along which the wafer is to be cut. At least one of the high energy beam or the wafer is moved in the direction of the cutting line so that the high energy beam passes over the wafer and penetrates the wafer to an intermediate depth along the length of the cutting line. The moving step is then repeated after each pass of the high energy beam over the wafer until the wafer is severed along the cutting path.

Abstract: A method for use in manufacture of field emitter devices is provided specifically for forming electron emitter tips in a doped semiconductor substrate. The method comprises the following steps: forming a depression around an emitter area in the substrate; doping the substrate in the depression; and expanding the dopant in the depression into the emitter area.

Abstract: A display is arranged in rows and columns with a current source for each column instead of a current source in each display cell. By omitting the current source from the cell, smaller display cell geometries are achieved. In a display where one row is selected at a time, the display of the present invention with smaller circuitry achieves performance identical to the prior art. Application is made to flat panel displays generally including field emission displays, liquid crystal displays, and integrated light emitting diode array displays.

Abstract: A matrix display maintains synchronization with an input NTSC composite video signal by combining the functions of a phase locked loop, a column selector, and a row selector. The matrix includes display cells arranged in rows and columns, each display cell enabled for display on receipt of a column pointer signal and a row pointer signal. The column selector includes a shift circuit that shifts a walking-one pattern to assert in turn one column pointer signal at a time for each column in the matrix. An overflow signal from the shift circuit is used for three functions: (1) to reinstate the walking pattern in the column selector, (2) to lock the phase locked loop on the horizontal synchronization pulse of the NTSC signal, (3) to clock the row selector. The row selector includes a shift circuit and walking-one pattern to assert in turn one row pointer signal for each row of the matrix.

Abstract: A monolithically integratable display apparatus for receiving a picture signal having frames of video information and horizontal and vertical synchronizing components includes a matrix of display cells arranged in an array of M rows by N columns. Display cells in the matrix are individually addressable by row and column signals so as to receive the video information in the picture signal in response thereto. A first shift circuit coupled to the matrix provides the row signals in response to a first clocking signal and a data signal. A second shift circuit coupled to the matrix provides the column signals in response to a second clocking signal. A first clock circuit, such as a phase locked loop, receives the horizontal synchronizing component of the picture signal and produces the second clocking signal in response thereto. A synchronizing detector circuit receives the vertical synchronizing component of the picture signal and produces the data signal in response thereto.

Abstract: A method for aligning and bonding spaced components, such as a baseplate and a faceplate of a field emission display, is provided. The method includes: providing an optical alignment tool suitable for flip chip bonding; calibrating the tool to simulate a desired spacing in the assembled components; aligning the components using the calibrated tool; bringing the aligned components towards one another using the calibrated tool; and then bonding the components together with the desired spacing therebetween. The method of the invention can be practiced with an aligner bonder tool calibrated to eliminate a parallax error. A spacer element placed between the bondheads of the tool can be used to simulate the desired spacing during calibration. Alternately the spacing during calibration can be simulated by measuring with a caliper or other instrument.

Abstract: A multi-stage process for preparing a phosphor product includes the stages of selecting precursors of a dopant and a host lattice as the phosphor starting materials, grinding the starting materials in an initial grinding stage for an initial grinding time period to produce an initial ground material having a smaller particle size distribution than the starting materials, firing the initial ground material in an initial firing stage at an initial firing temperature for an initial firing time period to produce an initial fired material, grinding the initial fired material in an intermediate grinding stage for an intermediate grinding time period to produce an intermediate ground material having a smaller particle size than the initial fired material, wherein the intermediate grinding time period is substantially less than the initial grinding time period, firing the intermediate ground material in an intermediate firing stage at an intermediate firing temperature for an intermediate firing time to produce an in