Abstract: A gate drive circuit and a display panel. The gate drive circuit includes one or more shift register groups. Each of the shift register groups includes N shift adjacent registers that output in sequence, with N being an integer greater than or equal to 3. Each of the shift registers includes a first output stage and a frequency division control module. The first output stage is configured to output a gate drive signal. The frequency division control module is configured to control outputting of the gate drive signal based on a refresh frequency. A control end of each frequency division control module in each of the shift register groups receives a control signal with a different phase and a same frequency, respectively, to adjust a pulse width of the gate drive signal and maintain a same pulse width at different refresh frequencies.

Abstract: A display panel is provided. The display panel includes an array substrate, a first electrode layer and a pixel definition layer. The first electrode layer includes a pixel electrode layer and an auxiliary electrode layer. The pixel definition layer includes a first opening and a second opening. The first opening is disposed in correspondence with the pixel electrode layer, and the second opening is disposed in correspondence with the auxiliary electrode layer. A side surface of the pixel electrode layer away from the array substrate is lower than a side surface of the auxiliary electrode layer away from the array substrate.

Abstract: The present application discloses a display panel including a quantity N of driver units that are cascaded. The quantity N of the driver units are arranged along a first direction. Each of the driver units includes a first output module, a signal generation module, and a second output module disposed along a second direction. The first output module is configured to output a first gate electrode driving signal. The second output module is configured to output a second gate electrode driving signal. The first gate electrode driving signal is different from the second gate electrode driving signal. The first output module includes a first buffer unit and a second buffer unit stacked on each other along a third direction. The present application stacks two buffer units in the first output module, which reduce a width of a frame occupied by the first output module while guaranteeing performance of transistors.

Abstract: A display panel, a manufacturing method thereof, and a mobile terminal are provided. The display panel includes a panel main body, a backboard, and a supporting layer sequentially stacked. Wherein, a shading thin film is disposed between the backboard and the supporting layer, and the shading thin film is laminated on one side of the backboard close to the supporting layer and/or on one side of the supporting layer close to the backboard.

Abstract: Provided is a display device having a thin profile and a high light use efficiency and a head-mounted display including the display device. The display device includes a display panel; a circular polarizer configured to convert display light from the display panel into circularly polarized light and to transmit the circularly polarized light; a patterning mirror including light transmitters and a light reflector, the light transmitters being configured to transmit the circularly polarized light and the light reflector being provided on a surface opposite to a surface facing the circular polarizer; a lens configured to transmit the circularly polarized light transmitted through the patterning mirror; and a circularly polarized light selective reflector configured to selectively reflect the circularly polarized light transmitted through the lens.

Abstract: An active matrix substrate includes a plurality of thin film transistors including an oxide semiconductor layer, an interlayer insulating layer, a plurality of pixel electrodes arranged above the interlayer insulating layer, a common electrode arranged between the pixel electrode and the interlayer insulating layer and also configured to function as a touch sensor electrode, a first dielectric layer arranged between the interlayer insulating layer and the common electrode, a second dielectric layer arranged between the common electrode and the pixel electrode, a plurality of touch wiring lines arranged between the interlayer insulating layer and the common electrode and formed of a third conductive film, and a plurality of pixel contact portions, in which each of the plurality of pixel contact portions includes a drain electrode of the thin film transistor, a connection electrode formed of the third conductive film and electrically connected to the drain electrode in a lower opening formed in the interlayer i

Abstract: A gate driving circuit includes a gate driving unit arranged in a multi-stage cascade. The gate driving unit includes a pull-up control module, a pull-up node, a first output module, a second output module, a pull-down control module, a first pull-down module, a pull-down node, a second pull-down module, and a pull-down maintenance module. The pull-up control module is configured to pull up a potential of the pull-up node under a control of a first clock signal input at a first clock signal input terminal. The pull-down control module is configured to pull up a potential of the pull-down node under a control of the first clock signal. The first pull-down module is configured to pull the potential of the pull-down node down to a potential of the first clock signal under a control of the potential of the pull-up node.

Abstract: A gate driving circuit includes gate driving units. Each of the gate driving units includes a node voltage control module and a pull-down module. The node voltage control module includes a first module and a storage module. The first module outputs a first voltage signal at a first node in response to a pull-down control signal at a first control port. The storage module includes a first port receiving the first voltage signal, and a second terminal electrically connected to the first node. The pull-down module outputs a first working signal for controlling a plurality of sub-pixels to turn off at an output port of the gate driving unit in response to the first voltage signal. The storage module maintains the first voltage signal applied on the first node to maintain the first working signal at the output port of the gate driving unit controlled by the pull-down module.

Abstract: Provided is an array substrate. The array substrate includes: a base substrate, and a plurality of gate lines, a plurality of data lines, a plurality of sub-pixels and a plurality of touch signal lines disposed on the base substrate. The data lines have a plurality of first extending parts and a plurality of second extending parts which are in an alternating arrangement. When the array substrate is used to prepare a liquid crystal display panel and the liquid crystal display panel is displaying, in each column of the sub-pixels, the voltage polarities of the two adjacent sub-pixels which respectively belong to two adjacent first pixel regions are opposite.

Abstract: An array substrate, a display panel, and a manufacturing method of the array substrate are provided, including a thin film transistor layer, a passivation layer, and a pixel electrode layer which are sequentially disposed on one above another. The passivation layer is provided with a first via hole and a second via hole staggered from each other. The pixel electrode layer includes a pixel electrode connected to a first conductive layer through the first via hole and the second via hole. Therefore, a problem of grayscale dark spots caused by the pixel electrode being broken at a connection point with the first conductive layer is avoided.

Abstract: A liquid crystal display device includes a display region including a first and second region adjacent in a first direction, a substrate with a width of the second region in the first direction being greater than a width of the first region, a plurality of first and second gate bus lines extending in a second direction and arranged in the first and second regions, and a first and second gate driver connected to the plurality of first and second gate bus lines, respectively. A first scanning period in which the first gate driver scans the first gate bus lines overlaps a part of a second scanning period in which the second gate driver scans the second gate bus lines.

Abstract: The present application discloses a gate drive circuit and a display panel. The gate drive circuit includes a plurality of cascaded gate drive units. Each of the gate drive units includes a stage transmission signal selection circuit, a pull-up control circuit, a pulse number reduction circuit, a first inversion circuit, a first output stage and a second output stage, and can output a second gate control signal with a greater number of pulses and a first gate control signal with a less number of pulses.

Abstract: A supporting component and a display device are provided. The supporting component is configured to support the display panel. The supporting component includes a hole. The supporting component includes a first support portion and a second support portion. The first support portion is arranged around the hole. The second support portion is arranged around the first support portion. An elasticity modulus of the second support portion is greater than an elasticity modulus of the first support portion.

Abstract: A liquid crystal display device includes a first substrate, a second substrate disposed more to a viewer side than the first substrate, and a liquid crystal layer provided between the first substrate and the second substrate, with a plurality of pixels being arrayed in a matrix shape. Each pixel includes a reflective region for display in a reflection mode. The first substrate includes a thin film transistor provided corresponding to each pixel, a pixel electrode electrically connected to the thin film transistor, and a reflective layer located at least in the reflective region. The first substrate further includes a common electrode adjacent to the pixel electrode with a dielectric layer interposed between the pixel electrode and the common electrode. At least one from among the pixel electrode and the common electrode includes at least one slit.

Abstract: A display panel and a display device are provided. At four corners of the display panel where a first inorganic layer and a second inorganic layer are attached, the display panel is defined with a through hole filled with a stress-buffering component. As a result, stresses on a bending area of the display panel are reduced by the stress-buffering component, and the display panel is prevented from breakage due to stress concentration.

Abstract: This application discloses a gate driving circuit and a display panel. The gate driving circuit includes a plurality of stage circuits. The stage circuit includes an input module, a first output module, a second output module, a voltage stabilizing module, and a first driving control module. The voltage stabilizing module includes a first transistor whose gate receives a clock signal. When the gate driving circuit operates in a low power consumption mode, the clock signal turns on the first transistor to reduce a power consumption of the gate driving circuit by reducing a frequency of the clock signal.

Abstract: The present invention discloses a display device, comprising: a camera, a display panel and a backplane. The display panel, located on the light incident side of the camera, includes a first display area and a second display area; wherein the second display area is arranged corresponding to the camera. The backplane, located between the camera and the display panel, includes a first backplane and a second backplane; wherein a vertical projection of the second backplane on the display panel covers at least the second display area, and the light reflectivity of the second backplane is less than the light reflectivity of the first backplane.

Abstract: A driving method for a display panel (100), and a display apparatus. The method includes: acquiring display data of a current frame and display data of a previous frame (S10); determining whether the display data of the current frame is the same as the display data of the previous frame (S20); if not, converting a default gray scale voltage corresponding to at least one sub-pixel among default gray scale voltages corresponding to a default gray scale bit number carried by the display data of the current frame into a target gray scale voltage of a target gray scale bit number, and driving the display panel (100) to display (S30).

Abstract: A solder-printing stencil and a method of printing solder paste are provided in the present application. A solder-printing stencil is used for printing a solder paste on a substrate in cooperation with a squeegee blade, the solder-printing stencil includes: a stencil body including a first region, a second region, and a third region, wherein the third region is defined between the first region and the second region, the third region is provided with a plurality of mesh holes spaced along a squeegeeing direction of the squeegee blade; and protruding portions are provided on a side of the stencil body facing the substrate, and the protruding portions are provided on both the first region and the second region.

Abstract: The present application relates to a display compensation method, including: performing an image identification process to display data to be compensated to obtain a display feature message; processing the display data to be compensated to obtain a display panel load coefficient; processing the display panel load coefficient and the display feature message to obtain a voltage drop compensation coefficient; and performing a compensation process to the display data to be compensated by the voltage drop compensation coefficient to obtain compensated display data to achieve compensation of display uniformity.