Abstract: A circuit for sound activity detection includes a transducer (106) adapted to generate an electrical signal based on detected sound; a variable gain amplifier adapted to amplify the electrical signal to generate an amplified electrical signal; a comparator adapted to compare the amplified electrical signal with at least one first threshold level to generate a comparison signal indicating comparator events; and a control circuit adapted to generate, based on the comparison signal, a gain control signal for controlling the gain of the variable gain amplifier, and a sound activity alert signal indicating the detection of sound activity.

Abstract: The invention concerns a computing system comprising: a plurality of islands capable of operating in one of a plurality of operating modes, a first island being coupled to a first island control circuit and a second island being coupled to a second island control circuit; a first mediation circuit coupled to the first and second island control circuits and adapted: to receive a first request from the first island control circuit to change a current operating mode of the first island; to receive a second request from the second island control circuit to change a current operating mode of the second island; and to control a first voltage supply circuit and/or a first clock generator to change a voltage and/or clock signal supplied to the first and second islands based on the first and second requests.

Abstract: The invention concerns a circuit for speech recognition comprising: a voice detection circuit configured to detect, based on at least one input parameter, the presence of a voice signal in an input audio signal and to generate an activation signal on each voice detection event; a speech recognition circuit configured to be activated by the activation signal and to perform speech recognition on the input audio signal, the speech recognition circuit being further configured to generate an output signal indicating, based on the speech recognition, whether each voice detection event is true or false; and an analysis circuit configured to generate, based on the output signal of the speech recognition circuit, a control signal for modifying one or more of said input parameters.

Abstract: The present invention concerns a method of protecting sensitive data, and a corresponding computing system processing device, comprising: entering, by a processing device, a sensitive date access mode in-which sensitive data is accessible; restricting, by a program running in the sensitive data access mode, one or more accessible address ranges for a non-secure function, and calling, from the sensitive data access mode, the non-secure function; and entering, by the processing device, a further operating mode to execute the non-secure function during which the processing device has access to only the one or more accessible address ranges.

Abstract: A memory circuit having: a control circuit of a line of a memory array including: a first transistor coupled between first and second nodes and controlled by a line selection signal including a high level and a low level; a second transistor controlled by a first signal and coupled between the first node and a voltage supply rail of a first supply voltage, the first supply voltage being higher than the high level of the line selection signal, the first node being coupled to a line of memory array, the second node receiving a timing signal; and a line deactivation circuit adapted to generate the first signal and including a reference cell and a level shifter.

Abstract: The invention concerns a circuit for speech recognition comprising: a voice detection circuit configured to detect, based on at least one input parameter, the presence of a voice signal in an input audio signal and to generate an activation signal on each voice detection event; a speech recognition circuit configured to be activated by the activation signal and to perform speech recognition on the input audio signal, the speech recognition circuit being further configured to generate an output signal indicating, based on the speech recognition, whether each voice detection event is true or false; and an analysis circuit configured to generate, based on the output signal of the speech recognition circuit, a control signal for modifying one or more of said input parameters.

Abstract: The invention concerns an amplifier circuit comprising: an amplifier having a first input coupled to an input node of the amplifier circuit via a first resistor and an output coupled to a load via a coupling capacitor, the output being coupled to the first input via a second resistor; and a current ramp generator adapted to supply a current ramp to the first input of the amplifier during a power up phase or power down phase of the amplifier circuit to control the rate of charge or discharge of the coupling capacitor.

Abstract: The invention concerns a memory cell having: first and second cross-coupled gated inverters (102, 104), each including first and second inputs (IN1, IN2) and an output (OUT) and being adapted to couple its output to a first logic level only when the first and second inputs both receive the inverse of the first logic level; a first cut-off circuit (106) coupling the second input (IN2) of the first gated inverter (102) to the first input (IN1) of the first gated inverter (102); and a second cut-off circuit (108) coupling the second input (IN2) of the second gated inverter (104) to the first input (IN1) of the second gated inverter (104).

Abstract: The invention concerns a memory cell having: first and second cross-coupled gated inverters (102, 104), each including first and second inputs (IN1, IN2) and an output (OUT) and being adapted to couple its output to a first logic level only when the first and second inputs both receive the inverse of the first logic level; a first cut-off circuit (106) coupling the second input (IN2) of the first gated inverter (102) to the first input (IN1) of the first gated inverter (102); and a second cut-off circuit (108) coupling the second input (IN2) of the second gated inverter (104) to the first input (IN1) of the second gated inverter (104).

Abstract: The invention concerns a memory array having memory cells arranged in columns and rows, the memory cells of each column being coupled to at least one common write line of their column, the memory cells of each row being coupled to a common selection line of their row, wherein each of the memory cells includes a latch formed of a pair of inverters cross-coupled between first and second storage nodes; a first transistor coupled between the first storage node and a first test data input; and a second transistor coupled between the second storage node and a second test data input.

Abstract: The invention concerns power supply circuitry for controlling a power-up phase of an islet of an integrated circuit, the circuitry having: a switch (102) controlled by a current and coupled between a supply voltage rail (104) and an internal voltage rail (105) of the islet.

Abstract: The invention concerns a memory array having memory cells arranged in columns and rows, the memory cells of each column being coupled to at least one common write line of their column, the memory cells of each row being coupled to a common selection line of their row, wherein each of the memory cells includes a latch formed of a pair of inverters cross-coupled between first and second storage nodes; a first transistor coupled between the first storage node and a first test data input; and a second transistor coupled between the second storage node and a second test data input.

Abstract: The invention concerns a computer implemented method of circuit conception of a clock tree (200) comprising: a plurality of pulse generators (202) each being coupled to the input of one or more pulsed latches and being arranged to generate a pulsed signal (PS); and a tree of buffers (204) for supplying a clock signal (CLK) to the pulse generators, the method comprising: the conception of the clock tree without pulse generators based on a timing analysis by the computer of the propagation of clock edges in the clock tree; and replacing by the computer in the clock tree at least one buffer, coupled to the input of each pulsed latch, by a pulse generator.

Abstract: The invention relates to a test device for an analog circuit to be mounted on a mixed circuit including said analog circuit and a synchronous digital circuit. The test device includes a disturbance emulator connected to a first supply source (UrefD) capable of disturbing a second supply source (UrefA) of the analog circuit, the first and second supply sources being optionally merged, the emulator being adapted for receiving data representative of the evolution, during a given duration, of the average (?I) and the typical deviation (?I) of a first inrush current (I) that would be applied to the first supply source by the digital circuit, and being adapted for applying to the first supply source during successive intervals, each successive interval having said duration, a second inrush current (Irep) equal to the sum of the average and of the product of the typical deviation and of a pseudo-random signal varying according to a Gaussian law.

Abstract: A switched-capacitor circuit including at least one first capacitor and a circuit for switching at least one armature of the first capacitor alternately to one and the other of two terminals at a switching frequency. The circuit further includes a second capacitor connected to the first capacitor at a node; and a filtering circuit connecting the node to a virtual ground only for frequencies belonging to a frequency range.

Abstract: The invention concerns a computer implemented method of circuit conception of a clock tree (200) comprising: a plurality of pulse generators (202) each being coupled to the input of one or more pulsed latches and being arranged to generate a pulsed signal (PS); and a tree of buffers (204) for supplying a clock signal (CLK) to the pulse generators, the method comprising: the conception of the clock tree without pulse generators based on a timing analysis by the computer of the propagation of clock edges in the clock tree; and replacing by the computer in the clock tree at least one buffer, coupled to the input of each pulsed latch, by a pulse generator.

Abstract: The invention concerns a supply circuitry system and method, including a supply circuitry arranged to control a power-up phase at the end of a sleep period of a circuit region of an integrated circuit, the supply circuitry comprising: first and second switches coupled between a supply rail and a supply node of the circuit region, the supply rail being coupled to receive a supply voltage (VDD) from a power supply unit; a comparator arranged to provide an output based on a comparison between a voltage at the supply node (VDD_INT) and a reference voltage (VREF); and control circuitry coupled to control terminals of the first and second switches and arranged to activate the first switch at the start of the power-up phase, and to activate the second switch once the output of the comparator indicates that the voltage at the supply node is greater than the reference voltage.

Abstract: The invention concerns a ROM comprising a set of memory points arranged in rows and columns, each memory point capable of storing two bits of data and comprising a single switch controllable to connect together first and second terminals of said switch, each of said first and second terminals being connected to one of first, second and third conductive lines, wherein said switch is connected via said first and second terminals between said first and second lines to encode a first data value, between said first and third lines to encode a second data value, between said second and third lines to encode a third data value, and both of said first and second terminals being connected to the same one of said first, second and third lines to encode a fourth data value.

Abstract: A method for simulating an electric circuit comprising components and receiving external stimuli, wherein the determination at a given time of the voltages at the circuit nodes comprises several iterations, each consisting of defining a probable voltage for each node, of calculating the currents of each component based on the component model, then of repeating until the mesh equation is verified, and wherein for the first time, a current of a component is calculated based either on the full accurate model, or on the simplified linear model, or on the compound model which is a fitting, according to the interval between the voltages at the component's terminals between the initial time and the first time, and the simplified, full or compound model is used respectively if the interval is smaller than a first threshold, greater than a second threshold or between the first and second thresholds.

Abstract: A switched-capacitor circuit including at least one first capacitor and a circuit for switching at least one armature of the first capacitor alternately to one and the other of two terminals at a switching frequency. The circuit further includes a second capacitor connected to the first capacitor at a node; and a filtering circuit connecting the node to a virtual ground only for frequencies belonging to a frequency range.