Abstract: A method of emulation or functional testing of a first microprocessor in its functional environment including one or several peripherals and at least one internal bus of communication between this first microprocessor and its peripherals, from a second microprocessor, consisting of deactivating the first microprocessor, using the communication bus(es) to communicate between the two microprocessors and the peripheral(s), and activating the second microprocessor, wherein the first microprocessor communicates with the second microprocessor over a series link and wherein the second microprocessor is realized by a simulation model.

Abstract: A device for testing an analog-to-digital converter providing a digital signal at a given sampling frequency, comprising a unit for providing a test signal to the converter, the test signal being a periodic signal comprising frequency components only at a fundamental frequency and at harmonics of the fundamental frequency, the fundamental frequency being a multiple of one quarter of the sampling frequency; a filter capable of receiving the digital signal and of rejecting the fundamental frequency to provide a filtered digital signal; and a unit capable of receiving the digital signal and the filtered digital signal and of providing a signal representative of the ratio between the effective powers of the digital signal and of the filtered digital signal.

Abstract: The invention concerns a ROM comprising a set of memory points arranged in rows and columns, each memory point capable of storing two bits of data and comprising a single switch controllable to connect together first and second terminals of said switch, each of said first and second terminals being connected to one of first, second and third conductive lines, wherein said switch is connected via said first and second terminals between said first and second lines to encode a first data value, between said first and third lines to encode a second data value, between said second and third lines to encode a third data value, and both of said first and second terminals being connected to the same one of said first, second and third lines to encode a fourth data value.

Abstract: A mixer receiving a first analog signal and a first digital signal, corresponding to a succession, at a first frequency, of first messages each comprising a first number of bits, and providing a second analog signal, comprises an analog-to-digital converter of the first analog signal into a second digital signal, corresponding to a succession, at a second frequency greater than the first one, of second messages having a second number of bits smaller than the first one; a digital-to-digital converter of the second digital signal into a third one corresponding to a succession, at the second frequency, of third messages having the first number of bits; an interpolation unit providing a fourth digital signal corresponding to a succession, at the second frequency, of fourth messages having the first number of bits; an adder providing the sum of the third and fourth digital signals; and an output digital-to-analog converter.

Abstract: A converter of a digital signal into a pulse-width modulated signal, comprising a first conversion unit receiving, at a first frequency, successive digital signals each having one of a first determined number of values, and providing first intermediary signals, at the first frequency, each having one of a second determined number of values smaller than the first determined number; a unit performing a decimation of the first intermediary signals to provide second intermediary signals at a second frequency equal to the first frequency divided by the second determined number minus one; and a second conversion unit providing at the second frequency, from the second intermediary signals, a two-state pulse-width modulated signal having a minimum duration in one of the two states which is equal to the inverse of the first frequency, the first conversion unit receiving the pulse-width modulated signal.

Abstract: A memory block comprising a network of memory cell rows and columns, each memory cell being connected to a word line and at least one bit line, in which at least two word lines are associated with each row, and at least two adjacent columns share at least one same bit line, two memory cells of the two adjacent columns belonging to a same row being connected to different word lines.

Abstract: The invention concerns a device for reading a storage cell (4), comprising a reading differential amplifier (18) having a first input terminal (16) connected to a column of cells (10) and a circuit (34) designed to feed to a second input terminal (20) of the amplifier (18) a reference voltage (Vref). The circuit (34) comprises means (38) for storing the voltage of said column and means (38, 40, 42) for applying as reference voltage (Vref) the stored voltage modified by a predetermined quantity.

Abstract: A ROM including a set of memory points arranged in rows and columns, in which each memory point, formed of a single controllable switch, memorizes an N-bit information, with N>=2. Each column includes 2N conductive lines; each of the two main terminals of each memory point is connected to one of said conductive lines, each information value being associated with a specific assembly of 2N connections from among the set of 22N possible connections; and each of N read means is provided to apply a precharge voltage to a chosen group of 2N−1 first lines, connect the 2N−1 other lines to a reference voltage, select a memory point, read the voltages from the first lines, combine the obtained results to provide an indication of the value of one of the bits of the information contained in the selected memory point.

Abstract: A method of fractional division of a frequency of a digital signal from N replicas of said digital signal shifted in phase with respect to one another by 2&pgr;/N. This method consists of selecting a first replica to generate the rising edge and a second replica to generate the falling edge, the first and second replicas of a period of the resulting signal being different from the first and second replicas used in the next period.

Abstract: The invention relates to an arrangement comprising a main amplifier (1, 10) and means (5) for creating, at least during predetermined periods, a floating references voltage (V.sub.G) for applying at least one input signal (V') on at least one first input terminal (E-, E) of the main amplifier, said reference voltage (V.sub.G) being servo-controlled to the equivalent input noise (Vn) of the main amplifier.

Abstract: A matrix memory array includes a P-type semiconductor substrate, thick oxide columns separating active columns, gate rows, a gate insulator interposed at the locations where these rows cover the active columns, N-type islands limited by the thick oxide columns and the gate rows, first conductive columns at the pitch of the active columns, constituting bit lines, second conductive columns at a pitch which is twice that of the first columns, constituting reference lines, and connections between each island and a first or second conductive column.

Abstract: A self-protected divider bridge in an integrated circuit comprising a P.sup.- substrate, a N.sup.- well, a P region forming a resistor, diffused in said well. A first and a second outmost contact and an intermediate contact are formed on the diffused region. A pad connected to the first contact receives an external voltage higher than the supply voltage of the integrated circuit. The reference potential of the integrated circuit is connected to the second contact and the substrate. A third contact formed on the well close to the first contact is connected to the first contact, and a fourth contact formed on the well close to the second contact is connected to the second contact.

Abstract: In a telephone system, several telephone terminals are connected to a single telephone line including several telephone interface circuits (6, 7, 8), each interface circuit being energized by ringing signals appearing on the line and being arranged between the telephone line (3) and one of the telephone terminals (13, 14, 15, 16), the ring of which is disconnected from the line. Each interface circuit comprises a circuit (26) for counting ringing signals and picking up the line, this first circuit receiving at the input the ringing signals appearing on the line (L1-L2) during a telephone call, and counting a predetermined number of these ringing signals, then picking up the line by a relay (27) at the moment the last ringing signal counted stops. The system is powered only by the signals on the telephone line.

Abstract: A line powered telephone interface circuit answers an incoming call and, responsive to a command tone, routes the call to a selected terminal. If no command tone is received within a predetermined time period, low voltage audio signalling devices located near the conventional telephone sets are activated to alert the subscriber of an incoming call. The interface need not be connected to a separated supply source. The device is connected to a telephone line and to at least one plug connectable with a telephone set jack, the device being connected to various terminals. A detector detects the ring signal and a relay establishes connection with a telephone line as soon as the ring signal has been detected for a determined time duration. A combination timer/switcher circuit inhibits the ringing of the corresponding telephone set, and is associated with a sound transducer connected operable by a low voltage signal.