Abstract: A complementary metal-oxide semiconductor (CMOS) image sensor and a method for fabricating the same are disclosed. The image sensor includes a sub-layer having a photodiode and a plurality of transistors formed thereon, a pad insulating layer formed on the sub-layer, a micro-lens formed on the pad insulating layer, the micro-lens including a first insulating layer having an uneven surface and a second insulating layer covering upper and side surfaces of a projected portion of the first insulating layer to form a dome shape, and a planarization layer formed on the micro-lens, and a color filter formed on the planarization layer.

Abstract: The method for forming a metal line stacking structure according to a preferred embodiment of the present invention comprises: sequentially forming a first barrier metal and a first metal layer on a lower dielectric layer that is disposed over a semiconductor substrate, and performing a plasma treatment; forming a second barrier metal on the plasma-treated first metal layer; selectively etching the second barrier metal, the first metal layer, and the first barrier metal to form a metal line layer including the second barrier metal, the first metal layer, and the first barrier metal, which respectively have a predetermined width; and sintering the metal line layer to raise a reaction between the first metal layer and the second barrier metal, thereby generating a metal compound layer.

Abstract: The method for forming a metal line stacking structure according to a preferred embodiment of the present invention comprises: sequentially forming a first barrier metal and a first metal layer on a lower dielectric layer that is disposed over a semiconductor substrate, and performing a plasma treatment; forming a second barrier metal on the plasma-treated first metal layer; selectively etching the second barrier metal, the first metal layer, and the first barrier metal to form a metal line layer including the second barrier metal, the first metal layer, and the first barrier metal, which respectively have a predetermined width; and sintering the metal line layer to raise a reaction between the first metal layer and the second barrier metal, thereby generating a metal compound layer.

Abstract: A method fabricating multiple wiring metals in a semiconductor device. The method includes forming a lower wiring metal on a semiconductor substrate, forming an interlayer dielectric on the lower wiring metal, and selectively removing the interlayer dielectric to form a contact dielectric film, a body dielectric film and an opening between the contact and body dielectric films. The method also includes filling the opening with low-k material, forming a capping dielectric on the contact and body dielectric films and the low-k material, forming a contact hole passing through the capping dielectric and the contact dielectric film to be connected to the lower wiring metal, and forming an upper wiring metal electrically interconnected to the lower wiring metal through the contact hole.

Abstract: A method for making a mask in a process of fabricating a semiconductor device is disclosed, in which one database is classified into an SRAM block and a random logic block so that OPC is separately performed for the SRAM block and the random logic block, thereby improving performance of the OPC. The method includes dividing an input database into an SRAM block and a random logic block, respectively performing optical proximity correction (OPC) for the SRAM block and the random logic block, and combining the SRAM block to the random logic block.

Abstract: A metal oxide semiconductor field effect transistor (MOSFET) is disclosed. The MOSFET includes a semiconductor substrate, a germanium layer formed by implanting germanium (Ge) ions into the semiconductor substrate, an epitaxial layer doped with high concentration impurities over the germanium layer, a gate structure on the epitaxial layer, and source/drain regions with lightly doped drain (LDD) regions in the semiconductor substrate. The germanium layer supplies carriers into the epitaxial layer so that short channel effects are reduced.

Abstract: A semiconductor device manufacturing method wherein a metal suicide layer is formed via an in-situ process. The method includes forming a gate electrode on a semiconductor substrate; forming an insulation side wall at either lateral surface of the gate electrode; forming a source/drain region in a surface of the semiconductor substrate at either side of the gate electrode; forming a metal layer on the surface of the semiconductor substrate including the gate electrode; performing a plasma treatment on the metal layer; forming a capping material layer on the metal layer; performing an annealing process upon the semiconductor substrate, to form a metal silicide layer on the surface of the semiconductor substrate at positions corresponding to the gate electrode and the source/drain region; and removing the capping material layer and the metal layer remained without reaction with the gate electrode and the semiconductor substrate.

Abstract: A CMOS image sensor and a method for fabricating the same in which color balance is enhanced by forming photodiodes to have a depth varied according to the wavelength of incident light to be received through a color filter layer. The predetermined depth varies, from shallow to deep, as the wavelength of the band of incident light increases, such that the predetermined depth is shallowest for the shortest wavelength, e.g., blue light, of the bands of incident light and is deepest for the longest wavelength, e.g., red, of the bands of incident light.

Abstract: A method of forming a metal line in a semiconductor device includes: forming a lower insulation layer for insulation from the lower substrate; forming a first metal line at a certain region on the lower insulation layer; sequentially forming a first oxide layer, an FSG (Fluorine-doped Silicate Glass) layer, and a second oxide layer on the lower insulation layer and the first metal line; removing the first oxide layer, the FSG layer, and the second oxide layer so as to expose the first metal line; forming an upper insulation layer on the lower insulation layer and the first metal line; forming a contact hole by etching the upper insulation layer to a degree that the first metal line is exposed; and forming a second metal line by depositing a metal material in the contact hole.

Abstract: A method for forming a shallow trench isolation (STI) in a semiconductor device, is presented. In one embodiment, the method includes successively forming a pad oxide and a pad nitride on a silicon substrate, successively etching the pad nitride, the pad oxide, and the silicon substrate to form a trench having a predetermined depth in the silicon substrate, and depositing a trench filling oxide to fill the trench. The method further includes polishing the trench filling oxide until the pad nitride is exposed, depositing a protective nitride to cover surface of the substrate including the pad nitride and the trench filling oxide, and isotropically etching the protective nitride and the pad nitride to form spacers.

Abstract: A CMOS image sensor and a method for fabricating the same are disclosed, in which double microlenses are formed using materials having different refractive indexes to improve concentration efficiency of light, thereby improving the characteristics of the image sensor.

Abstract: A nonvolatile memory device that effectively prevents the occurrence of the hump phenomenon as well as a manufacturing method for fabricating the same, is presented. In one embodiment, the nonvolatile memory device includes an insulating spacer formed at interface between the active region and isolation layer, and a charge trapping dielectric layer that is formed in the active region between the neighboring two insulating spacers. The device also includes a gate electrode layer formed on the charge trapping dielectric layer and a source and drain formed in the active region at both sides of the gate electrode layer.

Abstract: A flash memory cell transistor is presented that includes a stacked structure of successively formed tunnel oxide layer, floating gate, inter-gate insulating layer and control gate on a semiconductor substrate, an insulating thin film formed on a first sidewall of the stacked structure, and an access gate formed on the first sidewall of the stacked structure while interposing the insulating thin film. A drain region is formed in a first region of the substrate in which the first region is exposed by the floating gate and a source region is formed in a second region of the substrate in which the second region is exposed by the access gate. The access gate overlaps, along the vertical direction of the stacked structure, the control gate and the floating gate.

Abstract: A method for fabricating a semiconductor device is disclosed. The method prevents line contact defects and overhangs associated with a barrier metal layer. The method includes forming a PMD layer on a semiconductor substrate including a terminal for the semiconductor device and forming a first contact hole by removing the PMD layer positioned over the terminal of the semiconductor device. Ions are implanted in at least portions of the PMD layer corresponding to corners associated with the contact hole. The comers of the PMD layer are rounded by etching the portions of the PMD layer that correspond to the contact hole. A metal line is formed by depositing a metal layer on the PMD layer including the contact hole and selectively removing portions of the metal layer.

Abstract: The method for forming a metal line stacking structure according to a preferred embodiment of the present invention comprises: sequentially forming a first barrier metal and a first metal layer on a lower dielectric layer that is disposed over a semiconductor substrate, and performing a plasma treatment; forming a second barrier metal on the plasma-treated first metal layer; selectively etching the second barrier metal, the first metal layer, and the first barrier metal to form a metal line layer including the second barrier metal, the first metal layer, and the first barrier metal, which respectively have a predetermined width; and sintering the metal line layer to raise a reaction between the first metal layer and the second barrier metal, thereby generating a metal compound layer.

Abstract: A non-volatile memory device and a method of manufacturing the same where the non-volatile memory device is easily applicable to higher integration of a semiconductor device by reducing a cell size while assuring storage capacities required for operations of a device. The non-volatile memory device includes a semiconductor substrate in which an active region is defined by an isolation layer and a protruding portion is formed on the active region, a source region formed on the protruding portion, first and second gates formed at both sidewalls of the protruding portion and the source region, first and second drain regions formed in the active region at the outside of the first and second gates, and an insulation layer formed between the first and second gates and the protruding portion and the source region.

Abstract: An image sensor includes the steps of forming a sublayer including a photodiode, a transistor and a metal line on a substrate, forming a pattern layer on the sublayer to be overlapped with the photodiode and to having a curved surface, and forming a combined color filter and microlens on the pattern layer to have a curved surface.

Abstract: An image sensor and fabricating method thereof enable total photoelectric conversion without light loss by enhancing surface uniformity of a microlens in each area of the microlens. The method includes the steps of forming a sublayer including a photodiode, a thin film transistor and metal lines on a substrate including a pad area and a cell area, forming a first planarizing layer on the sublayer, forming a plurality of color separating layers on the first planarizing layer within the cell area, forming a second planarizing layer on the first planarizing layer including at least one of the plurality of color separating layers in the cell area, forming a plurality of microlenses on the second planarizing layer to overlap the plurality of color separating layers, respectively, and forming a capping layer on the second planarizing layer to fill gaps between the plurality of microlenses.

Abstract: A CMOS image sensor includes a photo sensing device for generating photo charges, a floating diffusion region for storing the photo charges generated by the photo sensing device therein, a transfer transistor connected between the photo sensing device and the floating diffusion region for transferring the photo charges generated by the photo sensing device to the floating diffusion region, a reset transistor connected between a supply voltage terminal and the floating diffusion region for discharging the charges stored in the floating diffusion region to reset the floating diffusion region, a drive transistor for acting as a source follower buffer amplifier in response to an output signal from the photo sensing device, a switching transistor connected to the drive transistor for performing an addressing operation, and a charge control device connected between the photo sensing device and the transfer transistor for controlling the amount of charges stored in the photo sensing device.

Abstract: A device for detecting contamination of a lens in an exposure device in which a sample for detecting contamination is formed of the same material as that of the lens and transmittance of the sample is detected to sense a contamination level of the lens.