Abstract: A method for detecting an abnormal condition of a MOS transistor in a subthreshold region. The method includes measuring a variation in a drain current with respect to a variation of a gate voltage of the MOS transistor to obtain a characteristics curve, and calculating, with reference to the obtained characteristics curve, a variation of transconductance with respect to each of the gate voltages to obtain a transconductance variable curve. The transconductance variable curve is differentiated. A number of inflection points in a curve obtained by the differentiation is determined to indicate the abnormal condition of the MOS transistor.

Abstract: A chain resistance pattern and a method of forming the same enable a test pattern to obtain maximum measurement results using minimum area and enable accurate detection of process errors. The chain resistance pattern includes an active layer for receiving an externally applied optical signal, a plurality of conductive layers sequentially stacked on the active layer to form a layer stack, a plurality of contacts, formed between each layer of the layer stack, to electrically connect each pair of adjacently disposed layers of the layer stack, and a pad connected to each layer of the layer stack.

Abstract: A manufacturing method of a double LDD MOS transistor includes forming a gate electrode on a semiconductor substrate; forming a first LDD area by implanting and thermally annealing impurity ions using the gate electrode as a mask; forming a first spacer on both lateral walls of the gate electrode; forming a second LDD area by implanting and thermally annealing impurity ions using the gate electrode and the first spacer as a mask; forming a second spacer on both lateral walls of the gate electrode and the first spacer; and forming a source-drain diffusion area by implanting and thermally annealing impurity ions using the gate electrode, the first spacer, and the second spacer as a mask.

Abstract: A semiconductor package device including a lead frame including a die pad to which a semiconductor chip is attached and a plurality of terminals for electrical interconnection of the semiconductor chip to an external device. The device also includes a plurality of bonding wires for electrically interconnecting the terminals to the semiconductor chip, a package body for protecting the semiconductor chip, die pad, terminals, and bonding wires, and a plurality of connections bonded to the terminals for electrically interconnecting the semiconductor chip to the external device. The plurality of connections are made of solder balls or bumps and electrically interconnected to board connectors of an external circuit board.

Abstract: A CMOS image sensor includes a plurality of photodiodes in a semiconductor substrate; an insulating interlayer on the semiconductor substrate including the plurality of photodiodes; a metal line in the insulating interlayer; a passivation layer on the insulating interlayer; an adhesive layer on the passivation layer; and a plurality of micro-lenses on the adhesive layer.

Abstract: An image sensor is disclosed where individual photo diodes of the respective unit cells separated by an element isolating layer are physically integrated into a single large scale pixel formed widely on a semiconductor substrate so as to hold the pixels in common. A pixel separation pattern is additionally formed on a portion of the large scale photo diode formed so as to electrically separate them. An optimization of the light receiving area of the photo diode, a minimization of the intrusion area of an element isolating layer, and so on are achieved, so that the photo diode recovers an area occupied by an intrusion of the element isolating layer, thus maximizing the light receiving area in an optimal scale and easily preventing electrical impacts between the respective unit cells.

Abstract: A CMOS image sensor and method for fabricating the same improve image characteristics by eliminating the thickness of a planarization layer.

Abstract: A method of manufacturing a semiconductor. A first epitaxial layer is formed on a gate nitride layer, and a protection nitride layer is formed on the first epitaxial and gate nitride layers. A first gate insulation layer is formed on a drain silicide, a gate oxide layer is formed on a portion of the first epitaxial layer exposed by a trench. A second epitaxial layer is formed on the first layer. Polysilicon fills the trench to form a gate electrode. Ion-implanting impurities on the second epitaxial layer forms a source region. A second gate insulation layer is formed on the gate electrode and the gate oxide layer, a source silicide is formed on the second gate insulation layer, and an interlayer insulation layer is formed on the second epitaxial layer, source region and source silicide. Source, gate and drain contact holes expose the source silicide, gate electrode and drain silicide.

Abstract: A method for making a mask in a process of fabricating a semiconductor device is disclosed, in which one database is classified into an SRAM block and a random logic block so that OPC is separately performed for the SRAM block and the random logic block, thereby improving performance of the OPC. The method includes dividing an input database into an SRAM block and a random logic block, respectively performing optical proximity correction (OPC) for the SRAM block and the random logic block, and combining the SRAM block to the random logic block.

Abstract: A cleaning method for removing copper-based foreign particles from a wafer. The method includes changing the zeta-potential of the copper-based foreign particles to negative and removing the copper-based foreign particles having negative zeta-potential by spin-scrubbing. Consequently, the quality of the semiconductor device and the yield thereof can be increased.

Abstract: A method of sequentially forming a silicide layer and a contact barrier in a semiconductor device is provided. In the method, a pre-metal dielectric layer is deposited over an underlying structure that has a silicon substrate, a gate electrode on the substrate, and source/drain regions in the substrate. Contact holes are formed toward the gate electrode and the source/drain regions in the dielectric layer. Then, a metal layer for the silicide layer is selectively deposited on the bottom of the contact holes by using ion implantation, for example. Thereafter, the contact barrier is conformally deposited on entire exposed surface, and a heat-treatment process is performed to form the silicide layer from the metal layer.

Abstract: A method for forming an intermetal dielectric layer in a semiconductor device using high density plasma chemical vapor deposition (HDP-CVD), and a semiconductor device manufactured thereby. The method includes the steps of: (a) forming a metal wiring including at least one via-hole by patterning a metal layer formed on a semiconductor substrate; (b) forming a nitride liner protecting the metal wiring; and (c) forming the intermetal dielectric layer on and between the metal wiring using HDP-CVD.

Abstract: Disclosed are a CMOS image sensor capable of improving the focusing capability of light and a method for manufacturing the same. The CMOS image sensor includes a plurality of first micro-lenses formed in the upper part of the planarization layer, each of the first micro-lenses arranged over a corresponding photodiode, and a plurality of second micro-lenses formed on the planarization layer, each of the plurality of second micro-lenses wrapping a corresponding first micro-lens respectively.

Abstract: A method of cleaning a silicon nitride layer on a substrate is provided to effectively remove negative-charged impurities such as polymer and particle from the silicon nitride layer. In the method, the zeta potential of the silicon nitride layer is changed from positive to negative, and then the silicon nitride layer is cleaned with a first solution selected from an alkali solution and an NC-2 solution. So the negatively-charged impurities can be easily removed due to a repulsion force. The substrate can be treated with spin scrubber or quick dump rinse before and/or after the changing of the zeta potential. To change the zeta potential, the substrate can be dipped into a second solution such as an SC-1 solution, an NC-2 solution, and an alkali solution.

Abstract: A method of forming a metal line in a semiconductor device including forming an inter-metal dielectric (IMD) layer on the semiconductor substrate including the predetermined pattern, planarizing the IMD layer through a first CMP process, and patterning a via hole on the planarized substrate. The method further includes depositing a barrier metal layer in the via hole, filling a refractory metal in an upper part of the barrier metal layer, planarizing the substrate filled with the refractory metal by performing a second CMP process, forming a refractory metal oxide layer by oxidizing a residual refractory metal region created by the second CMP process, and forming a refractory metal plug by removing the refractory metal oxide layer through a third CMP process.

Abstract: A semiconductor transistor device and a method for manufacturing the same are provided. The method includes forming a silicon epitaxial layer having a predetermined thickness in source and drain diffusion regions of a silicon semiconductor substrate and forming a source and drain junction by ion implantation and rapid annealing in the silicon semiconductor substrate in which the silicon epitaxial layer is formed. The semiconductor transistor device includes a silicon epitaxial layer formed to have a predetermined thickness in source and drain diffusion regions of a silicon semiconductor substrate. Thus, since a salicide layer is used without increase of leakage current, the transistor device having low power and high performance can be manufactured.

Abstract: A method for forming an isolation region in a semiconductor device such as a photodiode forms depletion layers at boundary regions between N-type regions of the photodiode and an ion injection layer in which P-type impurity ions are injected. Depletion layers are also formed between the N-type regions of the photodiode and a substrate of P-type semiconductor. Thus, depletion layers minimize a leakage current and eliminate interface defects. Low temperature processes are applied to prevent the impurity ions in the substrate from diffusing undesirably, thereby maximizing the pinning effect of the semiconductor device. The method includes steps of forming a trench region in a substrate; forming an ion injection layer by injecting impurity ions into an inner sidewall of the trench region; and forming an isolation region for a semiconductor device by filling the trench region with an undoped silicate glass film interposing the ion injection layer.

Abstract: A method of manufacturing a semiconductor device including forming a gate oxide layer, a first conductive layer, a capacitor dielectric layer, and a second conductive layer on a semiconductor substrate. The method also includes patterning the first and second conductive layers, the gate oxide layer, and the field oxide layer so as to form a gate pattern and a capacitor pattern; selectively wet-etching the first and second conductive layer so as to project out an outward part of the capacitor dielectric layer; implanting ions into the semiconductor substrate using the gate pattern and the protruding portion of the capacitor dielectric layer as an implantation mask; and removing the protruding portion of the capacitor dielectric layer so that the patterned capacitor dielectric layer has the same width as the gate electrode and the first capacitor electrode.

Abstract: A method of forming an aluminum contact including forming a barrier metal layer on an interlayer insulation layer pattern defining a contact hole, and forming an aluminum layer on the barrier metal layer so as to fill the contact hole. The method further includes forming a photoresist pattern for ion implantation, implanting ions into the aluminum layer, and annealing by using a rapid thermal process.

Abstract: A method for forming shallow trench isolation in a semiconductor device. The method includes forming a pad oxide and a pad nitride on a semiconductor substrate in successive order, forming a trench in the substrate by etching the pad nitride, the pad oxide and the substrate, removing a portion of the pad oxide to expose top corners of the trench, and rounding the exposed portion of the top corners of the trench by a wet chemical etch.