Abstract: Disclosed are a mask of a semiconductor device and a method for forming a pattern thereof, which is capable of correcting a line width bias between a long line width and a short line width when a mask of a semiconductor transistor is formed. The mask may include a plurality of rectangular light shielding patterns formed on a mask disc on which gate line and contact holes are formed; and a connection pattern composed of a plurality of division patterns for selectively connecting the plurality of rectangular light shielding patterns one another. The plurality of rectangular light shielding patterns overlap with the contact hole mask and are formed on both sides of the connection pattern. The connection pattern is divided into 3 to 7 division patterns.

Abstract: A method for manufacturing a semiconductor device is provided. The method includes the steps of forming an interlayer insulating layer on a semiconductor substrate, selectively patterning the interlayer insulating layer to form a contact hole, depositing a first metal on an inner surface of the contact hole, submerging the semiconductor substrate on which the first metal is deposited into an electrochemical plating (ECP) solution bath in which a second metal is dissolved, dissolving the first metal in the ECP solution bath, plating the first and second metals dissolved in the ECP solution bath at the same time to gap-fill an alloy of the first and second metals in the contact hole, and removing the alloy using the interlayer insulating layer as an end point in a CMP process to form an alloy interconnection.

Abstract: Disclosed are a gate structure in a trench region of a semiconductor device and method for manufacturing the same. The semiconductor device includes a pair of drift regions formed in a semiconductor substrate; a trench region formed between the pair of drift regions; an oxide layer spacer on sidewalls of the trench region; a gate formed in the trench region; and a source and a drain formed in the pair of the drift regions, respectively.

Abstract: A CMOS image sensor and a method for fabricating the same are disclosed, in which transfer characteristics are improved. The method includes forming a photodiode region and a second conductive type ion region on a surface of a first conductive type substrate by implanting a second conductive type impurity ion into an entire surface of the substrate where a transistor is to be formed, forming a second conductive type lightly doped ion region in the substrate corresponding to the photodiode region by lightly implanting a second conductive type impurity ion only in an area where the photodiode region is opened, and diffusing the second conductive type lightly doped ion region into the second conductive type ion region by a thermal process.

Abstract: A CMOS image sensor and method of manufacturing the same are provided. In one embodiment, the CMOS image sensor includes: an interlayer dielectric layer formed on a semiconductor substrate including a plurality of photodiodes and transistors; a plurality of color filter isolation layers formed on the interlayer dielectric layer; a color filter layer comprising a first color filter, a second color filter, and a third color filter formed on the interlayer dielectric layer, wherein a portion of the first color filter and a portion of the second color filter are formed on one of the plurality of color filter isolation layers, and wherein a portion of the second color filter and a portion of the third color filter are formed on another of the plurality of color filter isolation layers; and microlenses formed on the color filter layer.

Abstract: A first electrode layer having protrusions and depressions on its surface are formed on a lower insulating layer on a semiconductor substrate, and a sacrificial layer is formed on the first electrode layer with a material that is reflowable when heated. After reflowing the sacrificial layer by heat treatment, the reflowed sacrificial layer and first electrode layer are etched so that the protrusions of the first electrode layer are curved, and a dielectric layer and a second electrode layer are sequentially formed on the first electrode layer. When manufactured using the above method, a thin film capacitor may have higher capacitance without increasing the area of the electrode.

Abstract: A FinFET and a fabrication method thereof. The FinFET device includes an SOI substrate realized through a substrate, a buried oxide layer formed on the substrate, and a silicon epitaxial layer formed on predetermined areas of the buried oxide layer. A gate oxide layer is formed on the silicon epitaxial layer, and a gate electrode is formed on the gate oxide layer. A field insulator is formed on exposed areas of the buried oxide layer to thereby separate adjacent silicon epitaxial layers. Side surfaces of the silicon epitaxial layer are flattened through heat treatment. The fabrication method for a FinFET device includes forming the gate oxidation layer and the gate electrode on the SOI substrate; forming the mask pattern on the gate electrode; forming the trench by etching using the mask pattern as a mask; performing heat treatment to flatten the side surfaces of the silicon epitaxial layer; and forming the field insulator in the trench.

Abstract: A method for fabricating an STI gap fill oxide layer in a semiconductor device is provided. The method can include: forming a shallow trench for forming an STI on a semiconductor substrate; forming an STI liner oxide layer in the shallow trench for the STI; depositing an APCVD oxide layer at an upper portion of the STI liner oxide layer for an oxide layer gap fill in the shallow trench of the STI; d) performing a densifying annealing process to densify the APCVD oxide layer; and depositing an HDP-CVD oxide layer at an upper portion of the APCVD oxide layer so that the STI shallow trench is completely gap-filled.

Abstract: A flash memory device incorporating: a semiconductor substrate having an active region and a field region defined therein; a device isolation layer formed in the field region of the substrate; a floating gate having an edge portion overlapping the device isolation layer, the overlapped portion being etched back a depth about equal to a height of a protruding portion of the device isolation layer, the floating gate having a tunneling oxide layer interposed in the active region of the semiconductor substrate; and a gate insulation layer and a control gate sequentially formed on the floating gate.

Abstract: A method for manufacturing structures of a CMOS image sensor. The method comprises the steps of depositing a gate insulating layer and a conductive layer on a semiconductor substrate; depositing an ion implantation barrier layer on the conductive layer; patterning the deposited gate insulating layer, conductive layer and ion implantation barrier layer to form a patterned, composite gate insulating layer, gate electrode and ion implantation barrier structure; forming a second photosensitive layer pattern to define a photodiode region; and implanting low-concentration dopant ions into the substrate using the second photosensitive layer pattern as an ion implantation mask to form a low-concentration dopant region within the photodiode region.

Abstract: A method for fabricating a CMOS image sensor includes: forming a gate electrode on a pixel region of the semiconductor substrate and, at the same time, forming a polysilicon pattern on a middle resistor region; forming a first lightly doped n-type diffusion region on the photodiode region; forming a second lightly doped n-type diffusion region on the transistor region; consecutively forming first and second insulating layers on the entire surface of the semiconductor substrate; removing a predetermined portion of the second insulation layer on the transistor region and the middle resistor region; forming a third insulation layer on the entire surface of the semiconductor substrate; forming sidewalls of the first insulating layer and the third insulating layer on the gate electrode and the polysilicon pattern by performing an etch-back process; and heavily doping n-type impurities in the transistor region and the polysilicon pattern.

Abstract: A CMOS image sensor includes a semiconductor substrate with a first conductive type including a photodiode region and a transistor region, a gate electrode formed on the transistor region of the substrate, a first impurity region with a second conductive type formed in a portion of the semiconductor substrate between the photodiode region and the gate electrode, and a second impurity region with the second conductive type formed in the photodiode region of the semiconductor substrate.

Abstract: Disclosed is a semiconductor transistor for enhancing performance of PMOS and NMOS transistors, particularly current driving performance, while reducing a narrow width effect. A narrow width MOS transistor includes: a channel of which width is W0 and length is L0; an active area including source and drain areas formed at both sides with the channel as a center; a gate insulating layer formed on the channel; a gate conductor formed on the gate insulating layer and intersecting the active area; a first additional active area of width is larger than that W0 of the channel as an active area added to the source area; and a second additional active area of width is larger than that W0 of the channel as an active area added to the drain area. When the structure of the transistor having the additional active areas is applied to NMOS and PMOS transistors, a driving current is represented as 107.27% and 103.31%, respectively. Accordingly, the driving currents of both PMOS and NMOS transistors are enhanced.

Abstract: A semiconductor device includes an inter-metal dielectric (IMD) formed on a substrate and having at least one via hole, a via hole formed by filling the via hole with a first metal, a reductant layer formed on the via plug and the inter-metal dielectric to a predetermined thickness, and a metal line layer formed by depositing a second metal on the reductant layer.

Abstract: A sputtering apparatus for forming a low-resistance uniform metal silicide layer without additional heat treatment and a metal silicide layer forming method using the same are provided. The sputtering apparatus includes a sputtering chamber; a gas introduction port formed at an upper location of a lateral wall of the sputtering chamber; a gas exhaust port formed at a bottom wall of the sputtering chamber; a target located in an upper region of the sputtering chamber; a power source to supply the target with high-frequency electric power; a stage located in a bottom region of the sputtering chamber to heat the semiconductor substrate; and a sieve provided between the target and the semiconductor substrate to improve straightness of charged metal particles.

Abstract: A method for forming a metallization contact in a semiconductor device includes (a) forming an insulating layer on a semiconductor substrate including an active device region or a lower metal wire; (b) forming a contact hole to expose a portion of the active device region or lower metal wire by etching a portion of the insulating layer; (c) depositing a first TiN layer on the insulating layer and inside the contact hole by a PVD process using a first carrier gas composition of nitrogen (N2) and argon (Ar); (d) depositing a second TiN layer on the first TiN layer by a PVD process using a second carrier gas composition of nitrogen (N2) and argon (Ar); and (e) forming a metal layer on the second TiN layer.

Abstract: A semiconductor device and a method for manufacturing the same is provided. The semiconductor device includes a semiconductor substrate having a conductive layer; an interlayer dielectric layer formed on the semiconductor substrate, the interlayer dielectric layer having a hole with a taper angled at the hole's upper portion; a diffusion barrier layer formed on the hole and the interlayer dielectric layer; and a seed layer formed on the diffusion barrier layer.

Abstract: A method of manufacturing a semiconductor device is provided. The method includes the steps of forming a gate oxide layer including an oxide layer containing a large amount of nitrogen on a semiconductor substrate on which an input/output (I/O) region including an NMOS region and a PMOS region are defined, forming a polysilicon on the gate oxide layer, selectively removing the polysilicon on the PMOS region, selectively removing the gate oxide layer on the PMOS region, forming a pure SiO2 layer on the semiconductor substrate of the PMOS region, removing a surface oxide layer on the remaining polysilicon generated when the pure SiO2 layer is formed, and forming a gate electrode polysilicon on the entire surface including the remaining polysilicon.

Abstract: A semiconductor device and a method for fabricating the same is disclosed, in which one line is formed from a main gate to a sidewall gate, so that it is possible to scale a transistor below nano degree, and the semiconductor device includes a semiconductor substrate; a device isolation layer for dividing the semiconductor substrate into a field region and an active region; a main gate on a predetermined portion of the active region of the semiconductor substrate; a sidewall gate at both sides of the main gate on the semiconductor substrate; a main gate insulating layer between the main gate and the semiconductor substrate; a sidewall gate insulating layer between the sidewall gate and the semiconductor substrate; an insulating interlayer between the main gate and the sidewall gate; a first silicide layer on the surface of the main gate and the sidewall gate, to electrically connect the main gate with the sidewall gate; and source and drain regions at both sides of the sidewall gate in the active region of th

Abstract: A capacitor capable of being formed in a vertical plane without an additional mask process and/or deposition process and a method of manufacturing the same are provided. The capacitor includes: a first conductive line formed on a substrate; a first interlayer dielectric including a first via hole formed at an upper portion of the first conductive line, and a second and third via hole pair formed at a region of the substrate; a first barrier metal layer and a contact plug formed in the first via hole; and first and second capacitor electrodes formed in the second and third via holes, respectively. The first and second capacitor electrodes and the first interlayer dielectric disposed between the first and second capacitor electrodes form a vertically constructed capacitor.