Abstract: A voltage converter comprises an inductive circuit (L) for storing energy during an inductive magnetizing mode and transferring energy during an inductive demagnetizing mode. In addition the voltage converter comprises at least two non-inverting branches (12, 13, 14) for providing at least two non-inverted output voltages (Va, Vb, Vc) and an inverting branch (15) for providing an inverted output voltage. The inverting (15) and non-inverting (12, 13, 14) branches being parallely coupled to an output (10) of the inductive circuit (L). The inductive circuit being arranged to transfer energy to the inverting branch (15) and to one of the at least two non-inverting branches (12, 13, 14). Through this, the inverted voltage (Vinv) and the corresponding non-inverted output voltage (Va, Vb, Vc) of the one of the at least two non-inverting branches (12, 13, 14) are having an opposite polarity and a substantially equal magnitude.

Abstract: A MAC architecture for WLAN stations partitions functionality between a software-based MAC component and a hardware-based MAC component that work together to balance function and performance. In general, the fulcrum for this balance centers on timing requirements. Accordingly, the hardware-based MAC component is designed to handle many of the functions that are processor-intensive and/or must be performed under strict timing constraints. The software-based MAC component is designed to handle many of the functions that are memory-intensive, but present more lenient timing requirements. The software-based MAC component may be configured to provide an efficient and robust interface to the hardware-based MAC component. In particular, the software-based MAC component may format and prioritize packets to be sent over the air interface, and generate a command structure that provides instructions for the hardware-based MAC component to process the packet.

Abstract: The invention relates to a demodulator to demodulate frequency-modulated signals FM including a phase locked loop PLL including at least a phase detector, a loop filter and a voltage controlled oscillator function VCO?, characterized in that said voltage controlled oscillator function VCO? has modifiable gain. The invention allows to eliminate drawbacks presented by the conventional use of a complex gain modifiable amplifier at the input of demodulated signal processing means. Application: demodulation of modulated signals: wireless phone, home network.

Abstract: The integrated circuit according to the invention comprises a processor (603), a non-volatile memory (602) and an interface (605), where said interface (605) contains a first cache memory (601.1) and a second cache memory (601.2) and connects the processor (603) to the non-volatile memory (602). The interface (605) gets data from the non-volatile memory (602) and stores them in said first or said second cache memory (601.1, 601.2) intermediately and provides the processor (603) with data from said first cache memory (601.1) or from said second cache memory (601.2), depending on where the requested data are stored.

Abstract: Digital communication signals that encode information in the phase may be susceptible to phase error from many sources. A device corrects for carrier and sampling phase errors, as well as additive phase noise. A digital phase locked loop simultaneously tracks the carrier phase error and the sampling phase error, and corrects the signal in the frequency domain. The device may use the sampling phase error to advance or delay the sampling window used to convert the signal from the time domain to the frequency domain.

Abstract: The invention provides a receiver for use in a wireless communication system that substantially reduces mismatch between an in-phase (I) component and a quadrature (Q) component of a received signal. The receiver achieves this by sharing or “ping-ponging” an analog-to-digital converter (ADC) between the I and Q components. By sharing a single pipelined ADC between the I and Q components, both the I and Q components are processed by the same circuitry inside the pipelined ADC thereby eliminating many dominant sources of I-Q mismatch. The pipelined ADC operates at approximately twice the speed as other circuit components. Consequently, I-Q mismatch, which negatively affects performance, may be substantially reduced. At the same time, system complexity, cost, and power dissipation are reduced by eliminating an additional ADC typically used to process the I and Q components in parallel signal paths.

Abstract: Digital communication signals that encode information in the phase may be susceptible to phase error from many sources. The invention corrects for carrier and sampling phase errors, as well as additive phase noise. A digital phase locked loop simultaneously tracks the carrier phase error and the sampling phase error, and corrects the signal in the frequency domain. The invention may use the sampling phase error to advance or delay the sampling window used to convert the signal from the time domain to the frequency domain.

Abstract: The disclosure relates to an automatic level control technique for RF amplifiers in a communication system, such as a wireless communication system. The invention provides an automatic level control technique to compensate for variations in the gain of an RF amplifier, which may be a transmitter amplifier or a receiver amplifier. In accordance with the invention, the gain of the RF amplifier can be controlled as a function of the output of a voltage controlled oscillator (VCO) circuit provided in the communication system. A VCO typically includes a buffer amplifier with a structure similar to that of the RF amplifier used in the transmit or receive side of the RF front-end. By tracking changes in the output of the VCO buffer amplifier, an automatic level control (ALC) input to the RF amplifier can be adjusted to compensate for process- and temperature-based variations in amplifier gain.

Abstract: Architectures for decoding low density parity check codes permit varying degrees of hardware sharing to balance throughput, power consumption and area requirements. The LDPC decoding architectures may be useful in a variety of communication systems in which throughput, power consumption, and area are significant concerns. The decoding architectures implement an approximation of the standard message passing algorithm used for LDPC decoding, thereby reducing computational complexity. Instead of a fully parallel structure, this approximation permits at least a portion of the message passing structure between check and bit nodes to be implemented in a block-serial mode, providing reduced area without substantial added latency.

Abstract: A regulator circuit, embedded in a device, which is adapted to draw power from a power source internal to the device and a power source external to the device. The regulator circuit includes a first circuit segment for regulating power supplied by the internal power source, a second circuit segment for regulating power supplied by the external power source, an output circuit segment that monitors the output of the regulator circuit and supplies regulated power to the device. Additionally, responsive to the monitoring the regulator circuit preferentially draws power from the second circuit segment and complements the drawn power with power from the first circuit segment to maintain a regulated power supply at the output.

Abstract: In general, the disclosure is directed to techniques for enhancing power efficiency and linearity in an RF power amplifier. In accordance with the invention, a combination of different class power amplifiers is implemented in a parallel configuration to overcome the trade-off that exists between power efficiency and linearity. In particular, a class A amplifier and a class B amplifier are arranged in parallel to produce a combined amplifier output for an input signal. With bias voltages set to achieve a desired operating ratio between the class A and class B amplifier, the combined amplifier can provide a high power gain over a larger input range. In addition, the class B amplifier can provide increased power efficiency for larger inputs.

Abstract: In general, the invention is directed to a tunable inductor that makes use of eddy current effect to tune the inductance of an inductor. The tunable inductor may include a spiral or helical inductor in proximity to one or more sets of eddy current coils. Each eddy current coil may be coupled to a corresponding switch that controls whether the eddy current coil is grounded or floating. In operation, a first time-varying current through the inductor induces a first magnetic field that, in turn, induces a time-varying voltage in an eddy current coil. If the eddy current coil is not grounded, an eddy current flows through the eddy current coil. The eddy current, which flows in the opposite direction of the first time-varying current, induces a second magnetic field. The second magnetic field, which opposes the first magnetic field, reduces the inductance of the tunable inductor.

Abstract: A digital front-end for a wireless communication system incorporates gain control, signal detection, frame synchronization and carrier frequency offset (CFO) estimation and correction features configured for use with multiple receive antennas. The digital front-end may be applied to a wireless communication system in which transmitted signals carry a repeated signal pattern, such as orthogonal frequency division multiplexing (OFDM) systems. An example of a repeated signal pattern is the preamble of a signal transmitted according to the IEEE 802.11a wireless local area network (WLAN) standard. The signal detection, frame synchronization, and CFO estimation techniques make use of signals received from multiple antenna paths to provide enhanced performance. The gain control feature may be configured to adjust the gain in steps. The frame synchronization technique may operate as a function of gain control, handling the input signal differently before and after gain adjustment.

Abstract: A wireless communication technique enables equalization, soft demapping and phase error estimation functions to be performed jointly based on multiple observations of a transmitted symbol in wireless communication systems employing receive diversity. Multiple observations of a symbol are obtained from multiple antenna paths in a wireless receiver. Equalization, soft demapping and phase error estimation functions can be integrated within shared hardware, rather than distributed among separate hardware blocks, promoting reduced size, complexity and cost in a wireless receiver.

Abstract: The invention provides a receiver for use in a wireless communication system that substantially reduces mismatch between an in-phase (I) component and a quadrature (Q) component of a received signal. The receiver achieves this by sharing or “ping-ponging” an analog-to-digital converter (ADC) between the I and Q components. By sharing a single pipelined ADC between the I and Q components, both the I and Q components are processed by the same circuitry inside the pipelined ADC thereby eliminating many dominant sources of I-Q mismatch. The pipelined ADC operates at approximately twice the speed as other circuit components. Consequently, I-Q mismatch, which negatively affects performance, may be substantially reduced. At the same time, system complexity, cost, and power dissipation are reduced by eliminating an additional ADC typically used to process the I and Q components in parallel signal paths.

Abstract: An apparatus for dynamic diversity signal reception based upon receiver-side link quality assessments includes two or more antennae. At least one switch is connected to the two or more antennae. A dynamic diversity controller is connected to the at least one switch. The dynamic diversity controller includes a link quality assessor to assess link quality and generate a link characterization value. A diversity configuration selector, responsive to the link characterization value, selectively activates the at least one switch to implement a dynamic diversity configuration. The link quality assessor includes a signal strength analyzer, a modem detector, and/or a MAC layer analyzer to assess the received signal and generate the link characterization value.

Abstract: In general, the invention is directed to integration of passive radio frequency (RF) structures with at least one integrated circuit in a single integrated circuit (IC) package. An IC package in accordance with the invention may include, for example, a radio IC, a digital IC, a passive radio frequency balun as well as additional passive RF structures or ICs. Additionally, passive electronic components may further be incorporated in the IC package. For example, the IC package may include a resistor, capacitor, inductor or the like. The components of the IC package may be distributed throughout layers of a multi-layer IC package, such as a multi-layer ceramic package. The different ICs and the passive RF structures may be electrically coupled via conductive traces, which may be varied in thickness and length in order to match input and output impedances of the different ICs and passive RF structures.

Abstract: An apparatus for dynamic diversity signal reception based upon receiver-side link quality assessments includes two or more antennae. At least one switch is connected to the two or more antennae. A dynamic diversity controller is connected to the at least one switch. The dynamic diversity controller includes a link quality assessor to assess link quality and generate a link characterization value. A diversity configuration selector, responsive to the link characterization value, selectively activates the at least one switch to implement a dynamic diversity configuration. The link quality assessor includes a signal strength analyzer, a modem detector, and/or a MAC layer analyzer to assess the received signal and generate the link characterization value.

Abstract: A technique for enhanced frequency domain equalization in an OFDM communication receiver enables derivation of a more accurate estimate of channel gain fluctuation by adding an additional frequency tone observation to the estimate. For example, the technique may involve estimation of an unknown, complex, channel-induced gain A based on observation of complex amplitude values for first and second preamble symbols transmitted in an OFDM frame, plus the complex amplitude value for a signal field in the OFDM frame. The enhanced frequency domain equalization technique may be especially useful in a network conforming to the IEEE 802.11a standard.

Abstract: The invention provides a multi-band antenna structure for use in a wireless communication system. The antenna structure includes integrated inductive elements and capacitive elements that function as a tuned circuit to allow the antenna structure to operate in multiple frequency ranges. In particular, the capacitive elements electromagnetically couple to the inductive elements. The capacitive elements provide the inductive elements with parallel capacitance at a given set of frequencies, thereby providing the antenna structure with frequency selectivity. At a particular frequency range, the inductive elements act as short circuits, thereby lengthening the radiating elements, which radiate energy at the particular frequency. At another frequency range, the inductive components act as open circuits, virtually shortening the radiating elements in order to radiate the higher frequencies. In this manner, the multi-band antenna structure operates within multiple frequency ranges.