Abstract: A register file structure efficiently handles matrix and image processing. The register file contains an array of data elements and has modes for accessing of multiple data values that are aligned horizontally or vertically in a data array and for accessing data having different widths for each data value. The different modes allow manipulation of a transposed array without requiring a transpose operation and permit fast horizontal or vertical filtering with parallel access and multiplications of horizontally or vertically aligned data elements.

Abstract: A multiply unit uses four multipliers independently to perform for four parallel multiplications of single-width operands or uses the four multiplier cooperatively with an adder to perform a multiplication of double-width operands. In alternative embodiments, the adder operates in the same clock cycle as the multipliers or in a following clock cycle. Operand selection logic selects pairs of either single-width multiplicands or single-width partial multiplicands depending on for single or double-width multiplies.

Abstract: A system may include a control unit and a dual modulus prescaler. The control unit may generate a modulus control signal. The dual modulus prescaler may be configured to divide the frequency of an input signal by Q when the modulus control signal has a first value and to divide the frequency of the input signal by (Q+V) when the modulus control signal has a second value. Q is an irreducible fraction. The sum (Q+V) may be an integer or a fraction. The dual-modulus prescaler includes several clocked storage units (e.g., flip-flops) that are each clocked by a respective one of several equally spaced phases of the input signal. Each clocked storage unit operates in a toggle mode.

Abstract: A digital signal processor (DSP) includes at least two multipliers, at least two three-input arithmetic logic units (ALU), at least two first-cycle registers, at least two second-cycle registers, and multiplexing apparatus. The digital signal processor is able to perform a Fast Fourier Transform (FFT) calculation in two consecutive processing cycles.

Abstract: A phase-locked loop (PLL) includes a down counter having a detection circuit configured to determine when the counter reaches its terminal count. The down counter also includes a control line configured to alter the terminal count detected by the detection circuit by an off-set.

Abstract: A carrier-recovery loop for compensating frequency pulling in TDD and TDMA radio transceivers. The digital carrier-recovery loop includes a signal input, a digitally-controlled oscillator (DCO), a phase detector, a loop filter, and a memory. The memory stores an initializing value for the DCO, so that its frequency can be rapidly initialized at the start of a received frame. This initializing value is preferably either a sample of a control signal for the DCO, or a sample of the integrated value of a phase-error signal generated by the phase detector. Also described is a method for compensating the frequency pulling in a TDD or TDMA radio transceiver. The transceiver preferably receives data frames that have a preamble followed by a payload portion that holds the transmitted data.

Abstract: A processor made up of a computation unit, an accumulator unit, a saturation determination unit and a saturation unit. The computation unit operates on one or more operands of W bits. The accumulator unit stores the output of the computation unit, in W bits. The saturation determination unit detects overflow in parallel with latching of the output of the computation unit. Overflow occurs when the operand latched by the accumulator represents a number having more than A significant bits, where A is less than W. The saturation unit provides saturation operands to the computation unit when the operand latched in the accumulator unit represents a number having more than A significant bits. Furthermore, the processor has saturation operands of either (+2A−1−1) or −2A−1. A method for using the processor is also disclosed.

Abstract: A device for performing a search for the optimum code vector in a codebook having N code vectors indexed by i has a controller which considers each ith code vector, and a processor which determines in two clock cycles whether said ith code vector is the current optimal code vector.

Abstract: A memory array includes a memory unit and a dual access controller. The memory unit stores a multiplicity of words and has a plurality of word lines each of which accesses a row of words. The memory unit is divided into a left memory unit and a right memory unit, each having generally half of the storage space of the memory unit, the left memory unit having left half word lines and the right memory unit having right half word lines. The dual access controller receives a word address N and a word separation amount S and activates the columns and half rows of the memory unit in which a main word and a second word S words from the main word are found. In one embodiment useful for neighboring words, the left memory unit holds the words with even addresses and the right memory unit holds the words with odd addresses. In another embodiment, the left memory unit holds the first four words of an eight word set and the right memory unit holds the second four words.

Abstract: In a digital communication receiver, a system and method for recovering the timing of frames in the received signal. The receiver synchronizes an internal frame clock with a series of received data frames in the received data stream. One embodiment of a method for performing the frame synchronization proceeds by first recovering a symbol timing for data symbols in the received frames, then acquiring a frame timing by scanning the received data symbols for the SYNC field only during a narrow detection window around an expected location in time for the SYNC field, and then locking the frame timing. An embodiment of a system for performing the frame synchronization comprises an input for receiving the data frames in the received data stream, a symbol clock that indicates symbol transitions in the received data stream, timing logic that indicates the detection window during which the a SYNC field is expected, a SYNC-field detector, and a receiver frame clock.

Abstract: In a direct sequence spread spectrum communication receiver, a system and method for recovering the timing of a pseudo-random noise (PN) sequence used for despreading the received signals. In one embodiment of the method, the receiver waits for detection of a SYNC field to confirm at least a coarse synchronization or the receiver's local PN sequence with the received PN sequence (in the received signal). The receiver then performs a fast tracking to finely synchronize the receiver's PN sequence with the received PN sequence, preferably for a fixed duration of time. One embodiment of a system for performing the synchronization with the fast tracking includes an input for receiving a received spread-spectrum data stream, an ML detection logic, a receiver PN clock, a despreading mixer that generates a narrowband signal from the spread-spectrum data stream, a testing logic that generates a PASS output if it identifies a SYNC field in the narrowband signal, and a fast-tracking logic.

Abstract: A read only memory (ROM) which is made up of an array and a current sensing circuit. The array is made up of a number of cells each cell being adapted for storing N bits. Each cell has an operative element which is of one of 2N sizes representative of a combination of N bits. The current sensing circuit is connected to the array and senses the size of the operative elements of the array. The current sensing circuit thus differentiates between the 2N sizes of the operative elements to determine the values of each bit of the N bits in each cell. N is an integer greater than 1.

Abstract: In a direct sequence spread spectrum communication system, a system and method for recovering the timing of a pseudo-random noise (PN) sequence used for despreading the received signals. In one embodiment, the communication system is a time-division duplexing (TDD) or a time-division multiple-access (TDMA) system. A receiver in the communication system uses a “sliding correlator” maximal-likelihood (ML) detection system to scan through a range of possible PN phases to determine the correct one. In one embodiment of a method for performing the synchronization, a receiver acquires the PN phase by repeating the ML detection for a time greater than or equal to the period of the TDD or TDMA frames, with a sufficiently high repetition rate to ensure that the correct PN phase is examined at least once during a received frame. The acquisition is thereby completed within a fixed amount of time.

Abstract: In a direct sequence spread spectrum communication receiver, a system and method for recovering the timing of a pseudo-random noise (PN) sequence used for despreading the received signals. In one embodiment, the receiver performs a slow tracking to maintain the synchronization of the receiver's PN sequence with the received PN sequence. The slow tracking preferably includes one or more advancements or delays of the receiver's PN sequence if correlation measurements consistently indicate that the receiver's PN sequence lags or leads the received PN sequence. The slow tracking preferably also includes a long-term adjustment of the receiver's PN phase, distributed over a number of received frames, to compensate for any frequency offsets between the receiver's PN sequence and the received PN sequence.

Abstract: In a digital communications receiver, a system and method for evaluating the quality of received symbols and for initializing and adjusting a symbol clock. The invention presents a symbol quality detector that evaluates symbols which have been received by the receiver and detected in a matched filter. The received symbols are members of a constellation with elements that have purely I or purely Q components. The symbol-quality detector comprises inputs that receive the I and Q components of the symbols, and a logic block that generates the symbol-quality signal by constructing the quantity ||I|−|Q||. This quantity is a maximum when the detected symbols are aligned with the expected points in the symbol constellation, and decreases if the detected symbols are rotated away from these constellation points. The present invention further comprises a digital communications receiver that uses a symbol-quality detector to evaluate its symbol clock.

Abstract: A carrier-recovery loop for a receiver in a communication system with features that facilitate initialization of the loop. The carrier-recovery loop is a PLL that uses a feedback signal to keep a recovery oscillator phase-locked to the carrier of a received signal. In the present invention, an initializing value of the feedback signal is stored in a memory and provided to a digitally controlled recovery oscillator (DCO). This initializing value brings the recovered signal to an initial frequency that approximates the carrier frequency. When the receivers starts to acquire a phase-lock with the carrier, the carrier-recovery loop is in a condition close to the desired phase lock. Preparing the DCO in this manner imparts a significant improvement to the carrier-recovery loop. The response time for the loop to acquire a phase lock depends in part on its initial frequency offset from the carrier. In general, reducing this initial offset reduces the loop's acquisition time.

Abstract: A digital communications DQPSK passband detector having a matched filter, a differential decoder, and a slicer that use elementary circuit components. In the matched filter, recovered carrier reference signals are fed along with the received signal to a pair of XNOR gates. This arrangement effectively results in a multiplication operation without any complex circuit elements. The outputs of the XNOR gates control the direction of counting of a pair of binary counters that generate correlated values of the I and Q components in the received signal. Thus, the integrate/dump circuits of a conventional matched filter are replaced with simpler digital counters. A digital differential decoder to extract the phase difference information between two consecutive received symbols is built from a network of delay elements, multipliers, and adders to recover the phase data.

Abstract: A digital loop filter in the carrier-recovery loop of a digital communications receiver. The recovery loop is a PLL that keeps the receiver oscillator locked to the carrier wave, and the loop filter provides control over the PLL's frequency response by conditioning an error signal that is fed back to the receiver oscillator. In the present invention, the error signal is a digital signal, and the loop filter is implemented in digital hardware. With this implementation the characteristics of the loop filter are determined by logic design rather than by physical features of analog components, thereby giving this filter a more precise function than one with analog integrators. This implementation is also immune to the low tolerances typical of the manufacturing process for analog devices (especially on monolithic circuits), and is more easily adjusted than its analog counterparts. Two gain coefficients characterize the loop filter in the present invention.

Abstract: In a direct sequence spread spectrum digital communication receiver, a system and method for recovering and verifying the timing or phase of a pseudo-random noise (PN) sequence used for despreading received signals. In one embodiment, the method includes steps of: (a) determining an initial value of a received PN phase, (b) setting the receiver's PN phase equal to the initial value of the received PN phase, (c) a first testing to verify that the receiver identifies a SYNC field within a testing time of predetermined duration, (d) a second testing, to verify that temporarily shifting the receiver's PN phase results in a degraded correlation between the receiver's PN sequence and the received signal, and (e) repeating steps (a)-(d) if either of the testings indicate that the receiver's PN sequence is not correct.

Abstract: In a digital communication system for voice signals, a system and method for recovering the timing of a pseudo-random noise (PN) sequence used for direct-sequence spreading and despreading of the communicated signals. In one embodiment, a received signal is a time-division duplexing (TDD) or time-division multiple access (TDMA) signal, and a receiver performs a complete "sliding correlator" examination of the received signal in a fixed time by using the timing of the TDMA or TDD frames. This examination allows a rapid initial acquisition of the PN synchronization. In another embodiment of the receiver, the initially acquired PN phase is verified by reading a SYNC field from the received signal and by checking that shifting the receiver's local PN phase results in a degraded correlation between the local PN sequence and the received signal.