Patents Assigned to dSPACE digital signal processing and control engineering
  • Publication number: 20210124563
    Abstract: According to the invention, simulation code and production code are generated as source code from a model. The model comprises one or more blocks which specify a desired behavior of a program, in particular a control program. At least one of the blocks is marked with a simulation code attribute. Simulation code is generated for those blocks that include a simulation code attribute. Production code is generated for all other blocks. The generated source code includes both simulation code and production code. The simulation code portions are contained in the source code in a separable manner from the production code portions.
    Type: Application
    Filed: October 23, 2020
    Publication date: April 29, 2021
    Applicant: dSPACE digital signal processing and control engineering GmbH
    Inventors: Sebastian MOORS, Renata HEIN, Ulrich EISEMANN
  • Publication number: 20210081585
    Abstract: A method for event-based simulation of a system, the simulation comprising a first computing unit and at least one second computing unit, the first computing unit has a simulation time, the second processor has an operating system layer and an application layer. The second computing unit has a system time in the operating system layer, with at least the second computing unit executing a simulation application. At least one simulation object is executable on the simulation application, and the first computing unit manages an event queue, with at least one event per simulation step being listed in the event queue. The event is associated with a process to be executed by the simulation object and a simulation time provided for execution of the process.
    Type: Application
    Filed: November 17, 2020
    Publication date: March 18, 2021
    Applicant: dSPACE digital signal processing and control engineering GmbH
    Inventor: Stephan SCHEDLER
  • Publication number: 20210056432
    Abstract: A computer-implemented method for training an artificial neural generator network of generative adversarial networks for the purpose of approximating second test results from an identified subset of first test results of a virtual test of a device for at the least partial autonomous guidance of a motor vehicle. The invention also relates to a computer-implemented method for training an artificial neural discriminator network, a test unit, a computer program and a computer-readable data carrier.
    Type: Application
    Filed: August 21, 2020
    Publication date: February 25, 2021
    Applicant: dSPACE digital signal processing and control engineering GmbH
    Inventors: Sebastian BANNENBERG, Fabian LORENZ, Rainer RASCHE
  • Publication number: 20210034337
    Abstract: A method for preparing block diagrams having one or more blocks for code generation in a computing environment comprising a model editor, a data definition tool and a code generator. The block diagram is opened in the model editor, wherein a first block is a hierarchical block comprising a plurality of subordinate blocks, at least one input port and at least one output port connected by signals. Minimum values and maximum values are received for the input and output ports, determining scaling parameters for the input and output ports based on the received minimum and maximum values. Scaling parameters are determined for each subordinate block in the first block, wherein the scaling parameters of at least one subordinate block are determined based on the scaling parameters of at least one output port. Also, a method for generating program code, a non-transitory computer readable medium and a computer system are provided.
    Type: Application
    Filed: August 3, 2020
    Publication date: February 4, 2021
    Applicant: dSPACE digital signal processing and control engineering GmbH
    Inventors: Johannes SCHERLE, Anders JOHANSSON, Olaf GRAJETZKY
  • Patent number: 10909285
    Abstract: A method for creating a model of a technical system, is provided, the model being compatible with a simulation device. The simulation device is a simulation device set up for control unit development and the compatible model is executable on the simulation device. The method includes: providing a simulation-device-incompatible model of the technical system; providing a virtual execution environment, wherein the simulation-device-incompatible model of the technical system is executable in the virtual execution environment; and encapsulating the simulation-device-incompatible model of the technical system and the virtual execution environment in a compatible container unit forming the compatible model of the technical system. The incompatible model of the technical system can be addressable via the compatible container unit and the virtual execution environment on simulation device.
    Type: Grant
    Filed: December 18, 2017
    Date of Patent: February 2, 2021
    Assignee: dSPACE digital signal processing and control engineering GmbH
    Inventor: Andreas Pillekeit
  • Patent number: 10860298
    Abstract: A computer-implemented method for editing one or more properties of one or more model elements in a block diagram of a technical computing environment. The model elements include blocks and variables in blocks, wherein one or more properties are assigned to each model element. The technical computing environment has a model editor, a data definition tool and a code generator. A processor of a host computer opens a block diagram in the model editor, displays a list of model elements present in the block diagram, receives a selection of one or more model elements, highlights the selected model elements, receives an edit command to set a new value for a chosen property of the selected model elements, and sets the chosen property to the new value. A non-transitory computer readable medium and a computer system is also provided.
    Type: Grant
    Filed: November 6, 2018
    Date of Patent: December 8, 2020
    Assignee: dSPACE digital signal processing and control engineering GmbH
    Inventors: Torsten Pietzsch, Wolfgang Trautmann, Christian Witte
  • Patent number: 10860467
    Abstract: A configuration system for a test device designed for testing an electronic control unit. The test device is a hardware-in-the-loop simulator or a rapid control prototyping simulator, wherein a software model of a technical system is executed on the test device and the software model communicates electronically via an input/output interface of the test device with a system to be tested that is connected to the test device. Simulation data is electronically transmitted by the communication, and the configuration system is coupled to a modeling system and in the modeling system is a software model characterized by transversely and longitudinally connected function blocks. The configuration system configures the test device by interconnected configuration items such that the configuration items determine the physical characteristics of the input/output interface and/or the connection of the input/output interface with the software model.
    Type: Grant
    Filed: April 10, 2020
    Date of Patent: December 8, 2020
    Assignee: dSPACE digital signal processing and control engineering GmbH
    Inventors: Joerg Hagendorf, Martin Kronmueller
  • Publication number: 20200364392
    Abstract: A method for troubleshooting the program logic of a computer system. A first logic circuit and a first monitoring circuit, which is communicatively isolated from it, are programmed on a first programmable gate array of the computer system. A second logic circuit and a second monitoring circuit, which is communicatively isolated from it, are programmed on a second programmable gate array of the computer system. After an error has been detected in the program logic of the computer system, a first signal line, which applies a signal from the first logic circuit to a first signal input of the first monitoring circuit, is programmed in the first programmable gate array without changing the first logic circuit, and a second signal line, which applies a signal from the second logic circuit, is programmed in the second programmable gate array without changing the second logic circuit.
    Type: Application
    Filed: May 14, 2020
    Publication date: November 19, 2020
    Applicant: dSPACE digital signal processing and control engineering GmbH
    Inventors: Heiko KALTE, Dominik LUBELEY, Marc SCHLENGER
  • Publication number: 20200356399
    Abstract: A virtual control unit according to the AUTOSAR standard, including a service layer, an ECU abstraction layer, and a microcontroller abstraction layer. It is provided according to invention that the virtual control unit additionally comprises a hardware layer that is configured to simulate at least one hardware component. A virtual control unit is provided in this way which enables easy use of environment models for HIL tests and software testing and a fast simulation.
    Type: Application
    Filed: May 8, 2020
    Publication date: November 12, 2020
    Applicant: dSPACE digital signal processing and control engineering GmbH
    Inventors: Ulrich KIFFMEIER, Markus SUEVERN, Stuart Michael CHURCH
  • Patent number: 10805779
    Abstract: A computer-implemented method for implementing a V2X application on target hardware having a radio adapter, wherein the V2X application is modeled in the form of a block diagram by means of a graphical modeling environment and the block diagram is compiled into a V2X program that can be executed on the target hardware and the V2X program is transferred to the target hardware and executed there. The method for implementing a V2X application is realized in an especially simple and advantageous manner in that a V2X communication block that has at least one radio adapter interface, by means of which data are exchanged between the radio adapter and the V2X communication block, is used to create the block diagram.
    Type: Grant
    Filed: September 15, 2016
    Date of Patent: October 13, 2020
    Assignee: dSPACE digital signal processing and control engineering GmbH
    Inventors: Gregor Hordys, Andre Rolfsmeier
  • Patent number: 10795383
    Abstract: A method for regulating a volume flow rate, and a test stand with a liquid circuit for carrying out the method is provided. A pump and a flow control valve are connected in series in the liquid circuit, and the orifice width of the flow control valve is set as a function of a setpoint value of the volume flow rate of the liquid, in order to specify, on the basis of the orifice width, a characteristic curve of the pump that plots the volume flow rate over the differential pressure. Once a characteristic curve has been specified, the differential pressure of the pump is set such that the volume flow rate corresponds to the setpoint value of the volume flow rate.
    Type: Grant
    Filed: July 3, 2017
    Date of Patent: October 6, 2020
    Assignee: dSPACE digital signal processing and control engineering GmbH
    Inventor: Fabian Feilcke
  • Patent number: 10761814
    Abstract: A method for visualizing system models in a model management environment, which includes the steps of opening the system model in the model editor, receiving a user input for rescaling a block, determining a relative horizontal position and a relative vertical position for each port in the block, calculating a new absolute horizontal and vertical position of each port in the block based on the relative horizontal and vertical position and the new size preset for the block, and displaying the block and each port in the block.
    Type: Grant
    Filed: November 14, 2018
    Date of Patent: September 1, 2020
    Assignee: dSPACE digital signal processing and control engineering GmbH
    Inventors: Thomas Misch, Renate Loeffler, Joe Varghese
  • Patent number: 10747649
    Abstract: A method and device for transmitting metrologically acquired and digitized measured data in a test device. The measured data corresponds to a program task, and a direction of the transmission of the measured data from a measured data transmitter of the test device is provided via a data channel to a measured data receiver of the test device. The measured data transmitter has a signal preprocessing processor, a task monitoring processor and a data channel arbiter. Via the task monitoring processor, a task ID data packet is generated at an execution start of the program task or at an execution end of the program task, and the task ID data packet is transmitted to the data channel arbiter. Via the data channel arbiter, the measured data and the task ID data packet are successively forwarded via the data channel as a data stream to the measuring data receiver.
    Type: Grant
    Filed: June 4, 2018
    Date of Patent: August 18, 2020
    Assignee: dSPACE digital signal processing and control engineering GmbH
    Inventors: Matthias Fromme, Jochen Sauer, Matthias Schmitz
  • Publication number: 20200242018
    Abstract: A configuration system for a test device designed for testing an electronic control unit. The test device is a hardware-in-the-loop simulator or a rapid control prototyping simulator, wherein a software model of a technical system is executed on the test device and the software model communicates electronically via an input/output interface of the test device with a system to be tested that is connected to the test device. Simulation data is electronically transmitted by the communication, and the configuration system is coupled to a modeling system and in the modeling system is a software model characterized by transversely and longitudinally connected function blocks. The configuration system configures the test device by interconnected configuration items such that the configuration items determine the physical characteristics of the input/output interface and/or the connection of the input/output interface with the software model.
    Type: Application
    Filed: April 10, 2020
    Publication date: July 30, 2020
    Applicant: dSPACE digital signal processing and control engineering GmbH
    Inventors: Joerg HAGENDORF, Martin KRONMUELLER
  • Patent number: 10706196
    Abstract: A method for generating an FPGA implementation based on an FPGA design serving as an FPGA model and/or a hardware description, including the steps of synthesizing a net list from the FPGA design and generating the FPGA implementation from the net list. The method includes searching for a similar FPGA implementation, the step of generating the FPGA implementation from the net list takes place using the similar FPGA implementation, the method includes a step of generating a graph-based representation based on the FPGA design, and the step of searching for a similar FPGA implementation comprises comparing the graph-based representation of the FPGA design with a graph-based representation of the at least one similar FPGA implementation. A method for generating a bit stream based on an FPGA design is also provided, serving as an FPGA model and/or a hardware description.
    Type: Grant
    Filed: December 3, 2018
    Date of Patent: July 7, 2020
    Assignee: dSPACE digital signal processing and control engineering GmbH
    Inventors: Dominik Lubeley, Heiko Kalte
  • Publication number: 20200201608
    Abstract: A computer-implemented method for generating program code based on one or more blocks of a block diagram, at least one block including a block variable. The method comprises opening the block diagram in a model editor, retrieving generation settings for the block variable from a data definition tool, the generation settings comprising a scope of the variable, determining that a modification rule is referenced in the generation settings, and retrieving the referenced modification rule from the data definition tool, wherein a modification rule comprises a filter condition and one or more code changes. A processor generates program code based on the block diagram and the generation settings and applies the referenced modification rule to the block variable in the generated code, which includes verifying that the filter condition is fulfilled for the block variable and applying the code changes to each occurrence of the variable in the code.
    Type: Application
    Filed: December 21, 2018
    Publication date: June 25, 2020
    Applicant: dSPACE digital signal processing and control engineering GmbH
    Inventors: Lars WALLBAUM, Wolfgang TRAUTMANN
  • Patent number: 10678537
    Abstract: A method for generating a documentation of a program, the program being generated from one or more blocks of a block diagram in a technical computing environment, the one or more blocks of the program having at least one hierarchical block whose functionality is defined by a plurality of blocks in a subordinate hierarchical level of the block diagram. The method is carried out by a computer system having at least one processor, the processor opening the block diagram at a top hierarchical level in a model editor of the technical computing environment and verifying if a documentation condition is fulfilled for the current hierarchical level of the block diagram. When the documentation condition is fulfilled, the processor generates documentation text for the blocks in the current hierarchical level.
    Type: Grant
    Filed: November 20, 2017
    Date of Patent: June 9, 2020
    Assignee: dSPACE digital signal processing and control engineering GmbH
    Inventors: Renata Hein, Fabian Mogge
  • Patent number: 10671783
    Abstract: A method for generating an FPGA implementation based on an FPGA design serving as an FPGA model and/or a hardware description, including the steps of synthesizing a net list from the FPGA design and generating the FPGA implementation from the net list. The method includes searching for a similar FPGA implementation, the step of generating the FPGA implementation from the net list takes place using the similar FPGA implementation, the method includes a step of generating a graph-based representation based on the FPGA design, and the step of searching for a similar FPGA implementation comprises comparing the graph-based representation of the FPGA design with a graph-based representation of the at least one similar FPGA implementation. A method for generating a bit stream based on an FPGA design is also provided, serving as an FPGA model and/or a hardware description.
    Type: Grant
    Filed: December 3, 2018
    Date of Patent: June 2, 2020
    Assignee: dSPACE digital signal processing and control engineering GmbH
    Inventors: Dominik Lubeley, Heiko Kalte
  • Patent number: 10657037
    Abstract: A configuration system for a test device designed for testing an electronic control unit. The test device is a hardware-in-the-loop simulator or a rapid control prototyping simulator, wherein a software model of a technical system is executed on the test device and the software model communicates electronically via an input/output interface of the test device with a system to be tested that is connected to the test device. Simulation data is electronically transmitted by the communication, and the configuration system is coupled to a modeling system and in the modeling system is a software model characterized by transversely and longitudinally connected function blocks. The configuration system configures the test device by interconnected configuration items such that the configuration items determine the physical characteristics of the input/output interface and/or the connection of the input/output interface with the software model.
    Type: Grant
    Filed: August 31, 2018
    Date of Patent: May 19, 2020
    Assignee: dSPACE digital signal processing and control engineering GmbH
    Inventors: Joerg Hagendorf, Martin Kronmueller
  • Publication number: 20200150932
    Abstract: A method for visualizing system models in a model management environment, which includes the steps of opening the system model in the model editor, receiving a user input for rescaling a block, determining a relative horizontal position and a relative vertical position for each port in the block, calculating a new absolute horizontal and vertical position of each port in the block based on the relative horizontal and vertical position and the new size preset for the block, and displaying the block and each port in the block.
    Type: Application
    Filed: November 14, 2018
    Publication date: May 14, 2020
    Applicant: dSPACE digital signal processing and control engineering GmbH
    Inventors: Thomas MISCH, Renate LOEFFLER, Joe VARGHESE