Patents Assigned to eASIC Corporation
  • Patent number: 9704874
    Abstract: A bitline structure for use in a memory device may be connected to a plurality of bit memory cells. The bitline may be segmented into segments connected to one-third of the plurality of bit memory cells and two-thirds of the bit memory cells, respectively. The segments may be electrically coupled to each other to provide an overall bitline output.
    Type: Grant
    Filed: December 9, 2015
    Date of Patent: July 11, 2017
    Assignee: eASIC Corporation
    Inventors: Ban P. Wong, Hui Hui Ngu
  • Patent number: 9024657
    Abstract: A floorplan for a Structured ASIC chip is shown having a core region containing memory and VCLB logic cells surrounded by a plurality of IO connection fabrics that include a first IO connection fabric comprising IO sub-banks connecting the core of the chip to pins for external signals to the core, a first high-speed routing fabric disposed along the east-west vertical top of the core and connects the core to high-speed IO such as SerDes; a network-aware connection fabric connects the core to a microcontroller primarily for testing and repair of the memory in the core; and a second-high speed routing fabric is disposed on the north-south vertical sides of the core and communicates with the IO sub-banks. The VCLB Structured ASIC chip is manufactured on a 28 nm CMOS process lithographic node or smaller, having several metal layers and preferably is programmed on a single via layer.
    Type: Grant
    Filed: October 11, 2012
    Date of Patent: May 5, 2015
    Assignee: eASIC Corporation
    Inventors: Alexander Andreev, Ranko L. Scepanovic, Ivan Pavisic, Alexander Yahontov, Mikhail Udovikhin, Igor Vikhliantsev, Chong-Teik Lim, Seow-Sung Lee, Chee-Wei Kung
  • Patent number: 8957398
    Abstract: A via-configurable logic block architecture for a Structured ASIC has a plurality of MOSFET transistor chains connected to one another through vias. In one embodiment there are three chains and the first transistor chain is a NFET transistor chain, the second transistor chain is a PFET transistor chain, and the third transistor chain is a NFET transistor chain. The first, second and third transistor chains are formed into devices made of transistors that are selected from a voltage threshold group consisting of LVT, SVT and HVT devices, where the first and third transistor chains are formed into devices from a voltage threshold group that is different from one another. In another embodiment transistor drive strength may be varied in the transistor chains of the logic block. In yet another embodiment both voltage threshold and drive strength may be varied together in a symmetrical manner.
    Type: Grant
    Filed: October 11, 2012
    Date of Patent: February 17, 2015
    Assignee: eASIC Corporation
    Inventors: Alexander Andreev, Sergey Gribok, Ranko L. Scepanovic, Phey-Chuin Tan, Chee-Wei Kung
  • Patent number: 8848479
    Abstract: A memory system may provide for a successful write of a multi-port memory cell (e.g., dual-port 2WR SRAM cell) when it is simultaneously accessed by more than one port. This multi-port memory cell may include at least two independent accesses to the memory cell, where each access may be controlled by an independent wordline signal. Each port may have an independent pair of bitlines. Multiple write circuitry (e.g., double write circuitry) may enable the write driver to drive the input data to more than one pair of bitlines simultaneously.
    Type: Grant
    Filed: March 24, 2011
    Date of Patent: September 30, 2014
    Assignee: eASIC Corporation
    Inventors: Hui H. Ngu, Bruce Gieseke
  • Patent number: 8735857
    Abstract: A via-configurable circuit block may contain chains of p-type and n-type transistors that may or may not be interconnected by means of configurable vias. Configurable vias may also be used to connect various transistor terminals to a ground line, a power line and/or to various terminals that may provide connections outside of the circuit block.
    Type: Grant
    Filed: October 12, 2011
    Date of Patent: May 27, 2014
    Assignee: eASIC Corporation
    Inventors: Alexander Andreev, Sergey Gribok, Ranko Scepanovic
  • Publication number: 20140103985
    Abstract: A Digitally Controlled Delay Line (DCDL) for a Structured ASIC chip is used to delaying input or output signals into or out of core logic in a Structured ASIC. The DCDL has a multi-stage configuration that in a preferred embodiment comprises two fine delay stages for fine tuning the delay using sub-gate delay through an inverter whose delay can be adjusted with parallel CMOS transistors whose gates are biased with a voltage control signal that is thermometer coded. The fine-tune stages are followed by coarse delay stages that use gate-level delay. A DCDL controller outputs control signals that are Grey coded and converted to thermometer coded control signals by a Binary-to-Thermometer Decoder. The DCDL circuit block and accompanying Structured ASIC are manufactured on a 28 nm CMOS process lithographic node or smaller. A high speed routing fabric using a balanced binary tree is employed with the DCDL.
    Type: Application
    Filed: October 11, 2012
    Publication date: April 17, 2014
    Applicant: EASIC CORPORATION
    Inventor: eASIC Corporation
  • Publication number: 20140105246
    Abstract: A temperature control for a Structured ASIC chip, manufactured using a CMOS process is shown. A circuit employing temperature feedback using a microprocessor and active heating elements, that in a preferred embodiment uses decoupling cell capacitors, is employed to actively heat a die when the temperature of the die drops below a predetermined minimum temperature, in order to achieve timing closure in the chip.
    Type: Application
    Filed: October 11, 2012
    Publication date: April 17, 2014
    Applicant: eASIC CORPORATION
    Inventor: eASIC Corporation
  • Publication number: 20140103959
    Abstract: A floorplan for a Structured ASIC chip is shown having a core region containing memory and VCLB logic cells surrounded by a plurality of IO connection fabrics that include a first IO connection fabric comprising IO sub-banks connecting the core of the chip to pins for external signals to the core, a first high-speed routing fabric disposed along the east-west vertical top of the core and connects the core to high-speed IO such as SerDes; a network-aware connection fabric connects the core to a microcontroller primarily for testing and repair of the memory in the core; and a second-high speed routing fabric is disposed on the north-south vertical sides of the core and communicates with the IO sub-banks. The VCLB Structured ASIC chip is manufactured on a 28 nm CMOS process lithographic node or smaller, having several metal layers and preferably is programmed on a single via layer.
    Type: Application
    Filed: October 11, 2012
    Publication date: April 17, 2014
    Applicant: eASIC Corporation
    Inventor: eASIC Corporation
  • Patent number: 8677306
    Abstract: A network-fabric used for testing with an external or internal tester is shown for a Structured ASIC. In one embodiment, the Structured ASIC uses a microprocessor, network-aware IO routing fabric comprising network agents in a scalable novel configuration, with the network-aware IO having a plurality of blocks connected in series in a plurality of paths in the fabric leading to and from the microprocessor and memory and/or logic, the blocks acting as intelligent network agents under processor control to determine what state they can assume, whether to pass a data signal or not along these paths, comprising open loops and closed loops running to and from the microprocessor and memory and/or logic, primarily for testing and determining the state of the memory and logic. In another embodiment a JTAG controller may receive JTAG test commands from an external testing apparatus and set up to communicate along the fabric.
    Type: Grant
    Filed: October 11, 2012
    Date of Patent: March 18, 2014
    Assignee: EASIC Corporation
    Inventors: Alexander Andreev, Andrey Nikitin, Marian Serbian, Massimo Verita
  • Publication number: 20140028348
    Abstract: A via-configurable logic block architecture for a Structured ASIC has a plurality of MOSFET transistor chains connected to one another through vias. In one embodiment there are three chains and the first transistor chain is a NFET transistor chain, the second transistor chain is a PFET transistor chain, and the third transistor chain is a NFET transistor chain. The first, second and third transistor chains are formed into devices made of transistors that are selected from a voltage threshold group consisting of LVT, SVT and HVT devices, where the first and third transistor chains are formed into devices from a voltage threshold group that is different from one another. In another embodiment transistor drive strength may be varied in the transistor chains of the logic block. In yet another embodiment both voltage threshold and drive strength may be varied together in a symmetrical manner.
    Type: Application
    Filed: October 11, 2012
    Publication date: January 30, 2014
    Applicant: EASIC CORPORATION
    Inventor: EASIC CORPORATION
  • Patent number: 8629548
    Abstract: A clock architecture for a Structured ASIC chip, manufactured using a CMOS process is shown. A via-configurable logic block (VCLB) architecture in the Structured ASIC has a core region containing memory and logic cells arranged in columns that are supplied by a clock network having a global clock network tree and a low-level clock mesh to distribute the global clock signal in a repeating pattern. The clock mesh has a fishbone configuration in outline and allows for scalable expansion of the clock network. In one embodiment 36 global clocks may be provided to the Structured ASIC, with four clocks per logic cell. The VCLB Structured ASIC chip is manufactured on a 28 nm CMOS process lithographic node, having several metal layers but preferably is programmable on a single via layer.
    Type: Grant
    Filed: October 11, 2012
    Date of Patent: January 14, 2014
    Assignee: EASIC Corporation
    Inventors: Alexander Andreev, Andrey Nikishin, Sergey Gribok, Phey-Chuin Tan, Choon-Hun Choo
  • Patent number: 8504865
    Abstract: A clock signal may be aligned with a data signal by delaying the signals relative to each other until an edge of one signal aligns with an edge of the other signal, and then causing an inversion of the clock signal. A further variation may limit the relative delay period to one-half clock cycle and may use a double inversion of the clock signal.
    Type: Grant
    Filed: April 20, 2007
    Date of Patent: August 6, 2013
    Assignee: eASIC Corporation
    Inventors: Choon Keat Khor, Yeong Seng Hoo, Soon Chieh Lim
  • Patent number: 8436700
    Abstract: A MEMS-based switching device may be used to implement an interconnect switch in a programmable integrated circuit device. Such a MEMS-based device may include a deformable cantilever that may form a closed or open circuit to thereby implement switching functionality.
    Type: Grant
    Filed: September 18, 2009
    Date of Patent: May 7, 2013
    Assignee: eASIC Corporation
    Inventors: Herman Schmit, Sergey Gribok
  • Patent number: 8339844
    Abstract: A semiconductor device may be created using multiple metal layers and a layer including programmable vias that may be used to form various patterns of interconnections among segments of metal layers. The programmable vias may be formed of materials whose resistance is changeable between a high-resistance state and a low-resistance state.
    Type: Grant
    Filed: March 12, 2008
    Date of Patent: December 25, 2012
    Assignee: eASIC Corporation
    Inventors: Herman Schmit, Ronnie Vasishta, Adam Levinthal, Jonathan Park
  • Publication number: 20120243285
    Abstract: A memory system may provide for a successful write of a multi-port memory cell (e.g., dual-port 2WR SRAM cell) when it is simultaneously accessed by more than one port. This multi-port memory cell may include at least two independent accesses to the memory cell, where each access may be controlled by an independent wordline signal. Each port may have an independent pair of bitlines. Multiple write circuitry (e.g., double write circuitry) may enable the write driver to drive the input data to more than one pair of bitlines simultaneously.
    Type: Application
    Filed: March 24, 2011
    Publication date: September 27, 2012
    Applicant: EASIC CORPORATION
    Inventors: Hui H. Ngu, Bruce Gieseke
  • Publication number: 20120161093
    Abstract: A via-configurable circuit block may contain chains of p-type and n-type transistors that may or may not be interconnected by means of configurable vias. Configurable vias may also be used to connect various transistor terminals to a ground line, a power line and/or to various terminals that may provide connections outside of the circuit block.
    Type: Application
    Filed: October 12, 2011
    Publication date: June 28, 2012
    Applicant: eASIC Corporation
    Inventors: Alexander Andreev, Sergey Gribok, Ranko Scepanovic
  • Patent number: 8040739
    Abstract: A configurable memory system may be able to support at least three different write policies, namely, no-read-on-write, read-before-write, and read-after-write. Such a system may include configurable write signal timing, configurable read signal timing, and/or configurable wordline enable signal timing. Static and/or dynamic configuration of the system may be used.
    Type: Grant
    Filed: February 3, 2009
    Date of Patent: October 18, 2011
    Assignee: eASIC Corporation
    Inventors: Hui Hui Ngu, Choon Keat Khor
  • Publication number: 20110067982
    Abstract: A MEMS-based switching device may be used to implement an interconnect switch in a programmable integrated circuit device. Such a MEMS-based device may include a deformable cantilever that may form a closed or open circuit to thereby implement switching functionality.
    Type: Application
    Filed: September 18, 2009
    Publication date: March 24, 2011
    Applicant: eASIC Corporation
    Inventors: Herman Schmit, Sergey Gribok
  • Publication number: 20100195419
    Abstract: A configurable memory system may be able to support at least three different write policies, namely, no-read-on-write, read-before-write, and read-after-write. Such a system may include configurable write signal timing, configurable read signal timing, and/or configurable wordline enable signal timing. Static and/or dynamic configuration of the system may be used.
    Type: Application
    Filed: February 3, 2009
    Publication date: August 5, 2010
    Applicant: eASIC CORPORATION
    Inventors: Hui Hui Ngu, Choon Keat Khor
  • Patent number: RE46474
    Abstract: A memory system may provide for a successful write of a multi-port memory cell (e.g., dual-port 2WR SRAM cell) when it is simultaneously accessed by more than one port. This multi-port memory cell may include at least two independent accesses to the memory cell, where each access may be controlled by an independent wordline signal. Each port may have an independent pair of bitlines. Multiple write circuitry (e.g., double write circuitry) may enable the write driver to drive the input data to more than one pair of bitlines simultaneously.
    Type: Grant
    Filed: December 22, 2014
    Date of Patent: July 11, 2017
    Assignee: eASIC CORPORATION
    Inventors: Hui Hui Ngu, Bruce Gieseke