Abstract: A novel method is presented to provide ASICs with drastically reduced NRE and with volume flexibility. The invention includes a method of fabricating an integrated circuit, including the steps of: providing a semiconductor substrate, forming a borderless logic array including a plurality of Area I/Os and also including the step of forming redistribution layer for redistribution at least some of the Area I/Os for the purpose of the device packaging. The fabrication may utilize Direct Write e-Beam for customization. The customization step may include fabricating various types of devices at different volume from the same wafer.

Abstract: A semiconductor device may include a logic array having a multiplicity of inputs and a multiplicity of outputs and customized interconnections providing permanent direct interconnections among at least some of the multiplicity of inputs and at least some of the multiplicity of outputs.

Abstract: A configurable logic array may include: a multiplicity of logic cells, containing look-up tables; customizable metal and via connection layers overlying the multiplicity of logic cells; a multiplicity of device customizable I/O cells; a multiplicity of configuration customizable RAM blocks; a ROM block with customizable contents; and a microprocessor with customizable I/O for configuring and testing the array, where the customizations are all done on a single via layer.

Abstract: A configurable logic array may include: a multiplicity of logic cells, containing look-up tables; customizable metal and via connection layers overlying the multiplicity of logic cells; a multiplicity of device customizable I/O cells; a multiplicity of configuration customizable RAM blocks; a ROM block with customizable contents; and a microprocessor with customizable I/O for configuring and testing the array, where the customizations are all done on a single via layer.

Abstract: A logic array may include an array of programmable cells having a multiplicity of inputs and a multiplicity of outputs; and customized interconnections providing permanent direct interconnections among at least a plurality of the multiplicity of inputs and at least a plurality of the multiplicity of outputs.

Abstract: A logic array may include an array of programmable cells having a multiplicity of inputs and a multiplicity of outputs and customized interconnections providing permanent direct interconnections among at least a plurality of the multiplicity of inputs and at least a plurality of the multiplicity of outputs.

Abstract: A novel method is presented to provide ASICs with drastically reduced NRE and with volume flexibility. The invention includes a method of fabricating an integrated circuit, including the steps of: providing a semiconductor substrate, forming a borderless logic array including a plurality of Area I/Os and also including the step of forming redistribution layer for redistribution at least some of the Area I/Os for the purpose of the device packaging. The fabrication may utilize Direct Write e-Beam for customization. The customization step may include fabricating various types of devices at different volume from the same wafer.

Abstract: A logic array may include an array of programmable cells having a multiplicity of inputs and a multiplicity of outputs; and customized interconnections providing permanent direct interconnections among at least a plurality of the multiplicity of inputs and at least a plurality of the multiplicity of outputs.

Abstract: A novel method is presented to provide ASICs with drastically reduced NRE and with volume flexibility. The invention includes a method of fabricating an integrated circuit, including the steps of: providing a semiconductor substrate, forming a borderless logic array including a plurality of Area I/Os and also including the step of forming redistribution layer for redistribution at least some of the Area I/Os for the purpose of the device packaging. The fabrication may utilize Direct Write e-Beam for customization. The customization step may include fabricating various types of devices at different volume from the same wafer.

Abstract: A logic array may include an array of programmable cells having a multiplicity of inputs and a multiplicity of outputs and customized interconnections providing permanent direct interconnections among at least a plurality of the multiplicity of inputs and at least a plurality of the multiplicity of outputs.

Abstract: A logic array may include an array of programmable cells having a multiplicity of inputs and a multiplicity of outputs; and customized interconnections providing permanent direct interconnections among at least a plurality of the multiplicity of inputs and at least a plurality of the multiplicity of outputs.

Abstract: A logic array may include an array of programmable cells having a multiplicity of inputs and a multiplicity of outputs; and customized interconnections providing permanent direct interconnections among at least a plurality of the multiplicity of inputs and at least a plurality of the multiplicity of outputs.

Abstract: A personalizable and programmable integrated circuit device including at least first and second programmable logic cells and at least one permanent electrical conductive path interconnecting the at least first and second programmable logic cells for personalization of the integrated circuit device, wherein the at least first and second programmable logic cells are programmable by the application of an electrical signal thereto.

Abstract: A novel method is presented to provide ASICs with drastically reduced NRE and with volume flexibility. The invention includes a method of fabricating an integrated circuit, including the steps of: providing a semiconductor substrate, forming a borderless logic array including a plurality of Area I/Os and also including the step of forming redistribution layer for redistribution at least some of the Area I/Os for the purpose of the device packaging. The fabrication may utilize Direct Write e-Beam for customization. The customization step may include fabricating various types of devices at different volume from the same wafer.

Abstract: A personalizable and programmable integrated circuit device including at least first and second programmable logic cells and at least one permanent electrical conductive path interconnecting the at least first and second programmable logic cells for personalization of the integrated circuit device, wherein the at least first and second programmable logic cells are programmable by the application of an electrical signal thereto.

Abstract: A novel method is presented to provide ASICs with drastically reduced NRE and with volume flexibility. The invention includes a method of fabricating an integrated circuit, including the steps of: providing a semiconductor substrate, forming a borderless logic array including a plurality of Area I/Os and also including the step of forming redistribution layer for redistribution at least some of the Area I/Os for the purpose of the device packaging. The fabrication may utilize Direct Write e-Beam for customization. The customization step may include fabricating various types of devices at different volume from the same wafer.

Abstract: This invention discloses a method for designing and manufacturing semiconductors including the steps of: (i) producing a fab-ready design for a semiconductor device by importing into the design at least one core from a remote source, the core bearing an identification indicium, (ii) utilizing the fab-ready design to fabricate the semiconductor device, and (iii) reading the identification indicium from the semiconductor device to indicate incorporation of the at least one core therein.

Abstract: A personalizable and programmable integrated circuit device including at least first and second programmable logic cells and at least one permanent electrical conductive path interconnecting the at least first and second programmable logic cells for personalization of the integrated circuit device, wherein the at least first and second programmable logic cells are programmable by the application of an electrical signal thereto.

Abstract: This invention discloses a customizable logic array including an array of programmable cells having a multiplicity of inputs and a multiplicity of outputs; and customized interconnections providing permanent direct interconnections among at least a plurality of the multiplicity of inputs and at least a plurality of the multiplicity of outputs.

Abstract: This invention discloses a customizable and programmable integrated circuit device including at least first and second programmable logic cells, and at least two electrical conductive paths interconnecting the at least first and second programmable logic cells, at least a portion of which can be removed for customization of the integrated circuit device, wherein the at least first and second programmable logic cells are programmable by the application of an electrical signal thereto.