Abstract: A gallium nitride (GaN) transistor which includes multiple insulator semiconductor interface regions. Two or more first insulator segments and two or more second insulator segments are positioned between the gate and drain contacts and interleaved together. At least one first insulator segment is nearer to the gate contact than the second insulator segments. At least one second insulator segment is nearer to the drain contact than the first insulator segments. The first and second insulators are chosen such that a net electron donor density above the channel under the first insulator segments is lower than a net electron density above the channel under the second insulator segments. The first insulator segments reduce gate leakage and electric fields near the gate that cause high gate-drain charge. The second insulator segments reduce electric fields near the drain contact and provide a high density of charge in the channel for reduced on-resistance.

Abstract: A lateral power semiconductor device with a metal interconnect layout for low on-resistance. The metal interconnect layout includes first, second, and third metal layers, each of which include source bars and drain bars. Source bars in the first, second, and third metal layers are electrically connected. Drain bars in the first, second, and third metal layers are electrically connected. In one embodiment, the first and second metal layers are parallel, and the third metal layer is perpendicular to the first and second metal layers. In another embodiment, the first and third metal layer are parallel, and the second metal layer is perpendicular to the first and third metal layers. A nonconductive layer ensures solder bumps electrically connect to only source bars or only drain bars. As a result, a plurality of available pathways exists and enables current to take any of the plurality of available pathways.

Abstract: An integrated circuit that includes a plurality of GaN transistor sets. A first set of the plurality of GaN transistor sets includes transistors with a first drain-to-source distance, and wherein a second of the plurality of GaN transistor sets includes transistors with a second drain-to-source distance that is greater than the first drain-to-source distance.

Abstract: An enhancement mode GaN FET based gate driver circuit including an active pre-driver to drive a high-slew rate, high current output stage GaN FET. Due to the active driver current from the pre-driver, the output stage pull-up FET can turn on faster as compared to a pre-driver that utilizes a passive pull-up load. The active pre-driver must provide a voltage to drive the gate of the output stage pull-up FET which is higher than the normal supply voltage to enable the maximum output level of the driver FET to approach the normal supply voltage. A feedback circuit is included in the active pre-driver to avoid the need for two supply voltages.

Abstract: A highly efficient, multi-layered, single component sided circuit board layout design providing reduced parasitic inductance for power switched circuits. Mounted on the top board are one or more transistor switches, one or more loads, and one or more capacitors. The switches and capacitors form a loop with very low parasitic inductance. The loads may be a part of the loop, i.e. in series with the switches and capacitors, or may be connected to two or more nodes of the loop to form additional loops with common vertices. Parallel wide conductors carry the switch load current resulting in a low inductance path for the power loop. The power loop and gate loop current travel in opposite directions and are well separated, minimizing common source inductance (CSI) and maximizing switching speed.

Abstract: A common gate amplifier circuit configured to provide decreased voltage transients in the input voltage due to reverse gain. A second FET transistor is connected in series with a first FET of the common gate amplifier to function as an additional capacitive voltage divider between the amplifier output and the amplifier input without influencing the input or output currents. The first FET transistor, coupled to the amplifier input, may be a low voltage FET and smaller than the second FET transistor, which is coupled to the amplifier output. Both FET transistors are preferably enhancement mode GaN FET transistors and may be integrated into a single semiconductor chip with a single internal bias voltage divider.

Abstract: A current measurement circuit for determining a start time tSTART, an end time tEND, and/or a peak time tMAX for a current pulse passing through a current conductor. The current measurement circuit includes a pickup coil and a threshold crossing detector. The pickup coil generates a voltage VSENSE? proportional to a magnetic field around the conductor, which is proportional to a change in current over time. The threshold crossing detector compares VSENSE? and a threshold voltage and generates an output signal indicative of a transition time and whether a slope of VSENSE? is positive or negative. The current measurement circuit can also include an integrator and a sample and hold circuit. The integrator integrates VSENSE? over time and generates an integrated signal VSENSE. The sample and hold circuit compares VSENSE to tMAX and generates a second output signal which can be used to measure the pulse current.

Abstract: A large area wireless power system having a synchronization transmitter and a plurality of synchronization receivers for receiving a plurality of differential signals from the synchronization transmitter and outputting a plurality of second single-ended signals. The synchronization transmitter generates a first single-ended signal and converts the first single-ended signal into the plurality of differential signals to be transmitted to the synchronization receivers over a plurality of differential line pairs that also provide power to the synchronization receivers. The large area wireless power system also includes a plurality of high power amplifiers for receiving the plurality of second single-ended signals from the respective synchronization receivers and generating power, and a plurality of wireless power coils for receiving the power generated by the plurality of high power amplifiers and wirelessly providing power.

Abstract: A scalable highly resonant wireless power coil structure that is suitable for use across a large surface area. The structure includes a plurality of single turn loops with adjacent loops that are decoupled from each other, yet form part of a single member.

Abstract: A laser-diode driver for Lidar applications with an output stage comprised of two enhancement mode GaN FETs. The output stage includes a driver GaN FET in a traditional common-source configuration, with the drain connected to the cathode of a laser diode and the source connected to ground. The gate of the driver GaN FET is driven by the source of the second, substantially smaller GaN FET in a source-follower configuration, rather than being driven directly by a pre-driver. The source-follower GaN FET has its drain connected to the drain of the common-source driver GaN FET, similar to a Darlington connection used in bipolar devices. The input drive signal from the pre-driver is applied at the gate of the source-follower GaN FET. The current required to turn on the driver GaN FET is thereby drawn from a main power supply through the laser diode, rather than from the power supply for the pre-driver, improving overall current efficiency.

Abstract: A wireless power receiver circuit includes an active rectifier circuit with a plurality of power transistors, wherein the active rectifier circuit is configured to rectify an induced AC receiver current. The wireless power receiver circuit includes also includes a gate drive controller circuit configured to sense the induced AC receiver current and to provide gate drive signals for the plurality of power transistors synchronized with the induced AC receiver current. The gate drive controller circuit includes a current sense circuit configured to provide two voltage signals having a difference proportional to the induced AC receiver current.

Abstract: A current pulse generator circuit configured to be monolithically integrated into a single semiconductor die and provide high pulsing frequencies. A first GaN FET transistor controls the charging of a capacitor in a boost converter. A second GaN FET transistor controls the discharging of the capacitor through a load, such as a laser diode, connected to the boost converter. Both GaN FET transistors are preferably enhancement mode GaN FETs and may be integrated into the single semiconductor die, together with gate drivers. The diode in a conventional boost converter circuit can also be implemented in the present invention as a GaN FET transistor, and also integrated into the single semiconductor die.

Abstract: A cascaded bootstrapping gate driver configured to provide quick turn-on of a high side power FET and low static current consumption. The cascaded bootstrapping gate driver includes an initial bootstrapping stage with a resistor to decrease static current consumption during transistor turn-off. A secondary bootstrapping stage is driven by the initial bootstrapping stage and includes a GaN FET transistor with a low on resistance in place of the resistor. The source terminal of the GaN FET transistor provides a gate driving voltage to the high side power switch FET. The low on-resistance of the GaN FET transistor provides quick turn-on of the high side power FET. Transistors in the cascaded bootstrapping gate driver are preferably enhancement mode GaN FETs and may be integrated into a single semiconductor die.

Abstract: A power converter in which two power FETs are provided in a full bridge arrangement with two diodes for supplying a rectified voltage to a load. The gates of the power FETs receive alternating and opposite voltage waveforms such that the power FETs conduct oppositely to each other. A turn-off FET is connected to the gate of each power FET to prevent spurious turn on of the power FET during periods in which the opposite power FET is turned on. A voltage sense FET is also connected to the gate of each power FET to limit the gate voltage of the power FET. The voltage sense FETs are each synchronously modulated with the corresponding power FET to limit the gate to source voltage of the voltage sense FET when the corresponding turn-off FET is on and the corresponding power FET is off.

Abstract: A circuit for providing an adjustable output driver current for use in LiDAR or other similar GaN driver applications. The circuit creates an appropriate gate-to-source voltage, VGS, for a high-current GaN driver FET to obtain a desired, high slew-rate driver current, IDRV. An externally provided reference current is used to create the required VGS for the driver FET, which is stored on an external capacitor. The value of the capacitor far exceeds the relatively low input-capacitance of the GaN driver FET. When a pulse IDRV of desired value is needed, the voltage on the capacitor is impinged upon the gate of the driver FET, thereby creating the desired IDRV. The reference charging circuit replenishes any charge lost on the capacitor, so that the same desired IDRV can be obtained on the next command pulse.

Abstract: A direct-coupled level shifter to level shift a ground referenced input logic signal to an output logic signal that can have either a positive or negative reference. The level shifter includes two level shift drivers, each of which includes a positive level shift driver and a negative level shift driver. The positive level shift drivers operate when the reference of the latch is above ground and turn off when the reference is below ground. Similarly, the negative level shift drivers operate when the reference is below ground and turn off when the reference is above ground. The output logic signal is based on the output from the positive level shift driver receiving the input signal and the output from the negative level shift driver receiving an inverse of the input signal. The inverse of the output logic signal is based on the output from the positive level shift driver receiving an inverse of the input signal and the output from the negative level shift driver receiving the input signal.

Abstract: A driver shutdown circuit configured to trigger driver shutdown based on the magnitude and duration of the driving current. A first GaN FET is connected to a second GaN FET and an input node and generates a discharging current proportional to the driving current. The discharging current is drawn from a timer capacitor through the first and second GaN FETs. The second GaN FET receives a control signal and stops flow of the discharging current in between driver pulses so a pre-charger circuit can recharge the timer capacitor to a particular voltage. The discharging current drains the timer capacitor, and a shutdown signal generator outputs a shutdown signal to the driver in response to the voltage on the timer capacitor decreasing below a triggering voltage.

Abstract: A cascaded synchronous bootstrap supply circuit with reduced voltage drop between the cascaded bootstrap capacitors by replacing bootstrap diodes with gallium nitride (GaN) transistors. GaN transistors have a much lower forward voltage drop than diodes, thus providing a cascaded gate driver bootstrap supply circuit with a reduced drop in bootstrap capacitor voltage, which is particularly important as the number of levels increases.

Abstract: An enhancement-mode transistor gate structure which includes a spacer layer of GaN disposed above a barrier layer, a first layer of pGaN above the spacer layer, an etch stop layer of p-type Al-containing column III-V material, for example, pAlGaN or pAlInGaN, disposed above the first p-GaN layer, and a second p-GaN layer, having a greater thickness than the first p-GaN layer, disposed over the etch stop layer. The etch stop layer minimizes damage to the underlying barrier layer during gate etching steps, and improves GaN spacer thickness uniformity.

Abstract: An integrated DC-DC converter device includes a plurality of GaN transistor sets. A first set of the plurality of GaN transistor sets includes transistors with a first drain-to-source distance, and wherein a second of the plurality of GaN transistor sets includes transistors with a second drain-to-source distance that is greater than the first drain-to-source distance.