Abstract: Methods and circuits for extracting a true mean of two signals are provided. A first amplifier input stage (e.g., an n-type stage) is operated when a mean of the two signals approaches an upper rail voltage. A second amplifier input stage (e.g., a p-type stage) is operated when the mean of the two signals approaches a lower rail voltage. A transitioning circuit controls how much each of the first and the second amplifier input stages contributes to an input of a high-gain amplifier output stage, when the mean of the two signal does not approach either of the rail voltages. An output of the high-gain amplifier output stage is fed back to both the first and second amplifier input stages via a feedback stage, which can be a matched buffer stage.

Abstract: Improved systems and methods are provided for driving a column of display elements having a parasitic capacitance. Following a light emitting phase in a row time period, the column is partially discharged. During an initial phase within a next row time period, the column of display elements is pre-charged, if a light emitting phase is to be performed within the next row time period. Otherwise, the column of display elements is further discharged if a light emitting phase is not to be performed within the next row time period.

Abstract: A multiplexer circuit includes a plurality of switched differential amplifier circuits, one of which can be selected at a time. Each switched differential amplifier includes a pair of differential inputs and a pair of differential outputs, with each pair of differential inputs accepting a corresponding pair of input signals. Each of the switched differential amplifier circuits is configured to present a current mode version of its input signals at its differential outputs when the switched differential amplifier circuit is selected, and to present substantially zero level output signals at its differential outputs when the switched differential amplifier circuit is deselected. The multiplexer circuit also includes a selector that accepts a select signal and selects one of the plurality of switched differential amplifier circuits based on said select signal. A current mirror is used to combine a pair of multiplexer outputs into a single ended output, a version of which is used for feedback.

Abstract: A circuit for generating video synchronization timing signals includes a negative peak detector (FIG. 5) for following variations of a composite video signal (FIG. 1), rather than clamping the most negative voltage of the composite video signal. The negative peak detector provides a voltage level VTIP representative of the voltage at the synchronization tip of the composite video signal. A sample and hold circuit (700,702,704) is used to add an offset VSLICE to VTIP, VSLICE being a voltage level of the breezeway, color burst, or back porch segments of the composite video signal, or a combination of these segments. The sample and hold circuit generates a signal VREF, and is connected by a resistor divider (708,710) to the negative peak detector to form the signal VTIP+VSLICE provided to an amplifier (606) functioning as a comparator. The signal VSLICE+VTIP is compared in comparator (606) with the composite video signal to provide an overall circuit output.

Abstract: Differential amplifiers are provided that substantially cancel the input bias currents at the inputs to the differential amplifiers. A circuit produces a compensation current that is substantially equal in magnitude but opposite in polarity to input bias currents associated with the first and second inputs of the differential amplifier. A further pair of transistors are used to replicate the compensation current, and to provide replicated compensation currents to the inputs of the differential amplifier, thereby substantially canceling the input bias currents at the inputs.

Abstract: Circuits and methods for coherent noise cancellation are provided. More specifically, circuits and methods are provided for coherent cancellation of noise that is present in a data signal due to noise being present in the source signal (e.g., an optical signal) that is used to produce the data signal. The circuits, which use a subtraction process rather than division, are easy to implement in a chip, and provide for wide bandwidth performance.

Abstract: The analog demultiplexer (FIG. 6) includes an input amplifier (A1), and output amplifiers (AMP1–AMPN). The output and inverting (?) input of amplifiers (AMP1–AMPN) are connected by a respective capacitor (C1–CN). Switches (S1a, S1b, etc.) connect the output of amplifier (A1) to the inverting input of one of (AMP1–AMPN). Switches (S2a, S2b, etc.) connect the output of one of (AMP1–AMPN) to the non-inverting input of the amplifier A1. Switches (S2a, S2b, etc.) and (S1a, S1b, etc.) open and close together in pairs. With feedback from the output of (AMP1–AMPN) through (A1), the gain and any offset of (AMP1–AMPN) is divided down by the gain of (A1). Amplifier (A1) has capacitors (CS1 and CS2) connected to its inputs. Switch (S50) connects the inverting input of amplifier (A1) to its output, and switch (S40) connects the non-inverting input of (A1) to a voltage reference (VREF) matching (VREF) applied to (AMP2). Switches (S30) and (S35) connect (CS1) and (CS2) to the demultiplexer input (2).

Abstract: Circuits and methods for coherent noise cancellation are provided. More specifically, circuits and methods are provided for coherent cancellation of noise that is present in a data signal due to noise being present in the source signal (e.g., an optical signal) that is used to produce the data signal. The circuits, which use a subtraction process rather than division, are easy to implement in a chip, and provide for wide bandwidth performance.

Abstract: Current-mode preamplifiers are provided. In accordance with an embodiment, a current-mode preamplifier includes a transistor, that acts as an input stage for the preamplifier, and a pair of current mirrors. The transistor includes a gate connected to the input of the preamplifier, a source connected to a first voltage supply rail, and a drain. The first current mirror, which is connected to a second voltage supply rail, includes an input connected to the drain of the first transistor, and an output. The second current mirror, which is connected to the first voltage supply rail, includes an input connected to the output of the first current mirror, a first output connected to the input of the preamplifier, and a second output connected to the output of the preamplifier.

Abstract: A multiplexer circuit includes a plurality of switched differential amplifier circuits, one of which can be selected at a time. Each switched differential amplifier includes a pair of differential inputs and a pair of differential outputs, with each pair of differential inputs accepting a corresponding pair of input signals. Each of the switched differential amplifier circuits is configured to present a current mode version of its input signals at its differential outputs when the switched differential amplifier circuit is selected, and to present substantially zero level output signals at its differential outputs when the switched differential amplifier circuit is deselected. The multiplexer circuit also includes a selector that accepts a select signal and selects one of the plurality of switched differential amplifier circuits based on said select signal. A current mirror is used to combine a pair of multiplexer outputs into a single ended output, a version of which is used for feedback.

Abstract: An output stage for a Class-G amplifier includes four current mirrors, (CmpL) powered by a first low voltage supply (VspL), (Cmph) powered by a first high voltage supply (Vsph), (CmmL ) powered by a second low voltage supply (VsmL), and (Cmmh) powered by a second high voltage supply (Vsmh). The outputs of the current mirrors are connected together to form an output of the output stage. A buffer (10), whose input forms an input to the output stage, includes a first transistor (19) and a second transistor (27) connected in an emitter follower configuration, which are used to steer the buffer's output either through the first transistor (19) to a first switch (69) or through the second transistor (27) to a second switch (84). The first switch (69), which is controlled by a first comparator (68) connects a collector of the first transistor (19) to either the input to the first current mirror (CmpL) or the input to said second current mirror (Cmph).

Abstract: A circuit for generating video synchronization timing signals includes a negative peak detector (FIG. 5) for following variations of a composite video signal (FIG. 1), rather than clamping the most negative voltage of the composite video signal. The negative peak detector provides a voltage level VTIP representative of the voltage at the synchronization tip of the composite video signal. A sample and hold circuit (700, 702, 704) is used to add an offset VSLICE to VTIP, VSLICE being a voltage level of the breezeway, color burst, or back porch segments of the composite video signal, or a combination of these segments. The sample and hold circuit generates a signal VREF, and is connected by a resistor divider (708,710) to the negative peak detector to form the signal VTIP+VSLICE provided to an amplifier (606) functioning as a comparator. The signal VSLICE+VTIP is compared in comparator (606) with the composite video signal to provide an overall circuit output.

Abstract: Differential amplifiers are provided that substantially cancel the input bias currents at the inputs to the differential amplifiers. A circuit produces a compensation current that is substantially equal in magnitude but opposite in polarity to input bias currents associated with the first and second inputs of the differential amplifier. A further pair of transistors are used to replicate the compensation current, and to provide replicated compensation currents to the inputs of the differential amplifier, thereby substantially canceling the input bias currents at the inputs.

Abstract: Current-mode preamplifiers are provided. In accordance with an embodiment, a current-mode preamplifier includes a transistor, that acts as an input stage for the preamplifier, and a pair of current mirrors. The transistor includes a gate connected to the input of the preamplifier, a source connected to a first voltage supply rail, and a drain. The first current mirror, which is connected to a second voltage supply rail, includes an input connected to the drain of the first transistor, and an output. The second current mirror, which is connected to the first voltage supply rail, includes an input connected to the output of the first current mirror, a first output connected to the input of the preamplifier, and a second output connected to the output of the preamplifier.

Abstract: Current output stages are provided. In accordance with an embodiment, a current output stage includes a voltage follower circuit, a first current mirror and a second current mirror. A node of the voltage follower circuit provides a voltage that follows a voltage at the output of the current output stage. An input of the first current mirror is connected (e.g., by a current path of a transistor) to the node of the voltage follower circuit that follows the voltage at the output of the current output stage. An output of the first current mirror is connected to an input of the second current mirror. An output of the second current mirror is connected to the input of the current output stage.

Abstract: Circuits and methods for coherent noise cancellation are provided. More specifically, circuits and methods are provided for coherent cancellation of noise that is present in a data signal due to noise being present in the source signal (e.g., an optical signal) that is used to produce the data signal. The circuits, which use a subtraction process rather than division, are easy to implement in a chip, and provide for wide bandwidth performance.

Abstract: An output stage for a Class-G amplifier includes four current mirrors, (CmpL) powered by a first low voltage supply (VspL), (Cmph) powered by a first high voltage supply (Vsph), (CmmL ) powered by a second low voltage supply (VsmL), and (Cmmh) powered by a second high voltage supply (Vsmh). The outputs of the current mirrors are connected together to form an output of the output stage. A buffer (10), whose input forms an input to the output stage, includes a first transistor (19) and a second transistor (27) connected in an emitter follower configuration, which are used to steer the buffer's output either through the first transistor (19) to a first switch (69) or through the second transistor (27) to a second switch (84). The first switch (69), which is controlled by a first comparator (68) connects a collector of the first transistor (19) to either the input to the first current mirror (CmpL) or the input to said second current mirror (Cmph).

Abstract: A method and apparatus for generating reference voltages for a flat panel display system includes using a digital to analog converter (DAC) to supply multiple reference voltages to the flat panel display system, and wherein the DAC is adapted to accept digital input voltage reference from one of a plurality of registers and is adapted to provide an analog output to a demultiplexer, which includes a plurality of selectable sample and hold circuits.

Abstract: Methods and circuits for extracting a true mean of two signals are provided. A first amplifier input stage (e.g., an n-type stage) is operated when a mean of the two signals approaches an upper rail voltage. A second amplifier input stage (e.g., a p-type stage) is operated when the mean of the two signals approaches a lower rail voltage. A transitioning circuit controls how much each of the first and the second amplifier input stages contributes to an input of a high-gain amplifier output stage, when the mean of the two signal does not approach either of the rail voltages. An output of the high-gain amplifier output stage is fed back to both the first and second amplifier input stages via a feedback stage, which can be a matched buffer stage.

Abstract: The analog demultiplexer (FIG. 6) includes an input amplifier (A1), and output amplifiers (AMP1-AMPN). The output and inverting (?) input of amplifiers (AMP1-AMPN) are connected by a respective capacitor (C1-CN). Switches (S1a, S1b, etc.) connect the output of amplifier (A1) to the inverting input of one of (AMP1-AMPN). Switches (S2a, S2b, etc.) connect the output of one of (AMP1-AMPN) to the non-inverting input of the amplifier A1. Switches (S2a, S2b, etc.) and (S1a, S1b, etc.) open and close together in pairs. With feedback from the output of (AMP1-AMPN) through (A1), the gain and any offset of (AMP1-AMPN) is divided down by the gain of (A1). Amplifier (A1) has capacitors (CS1 and CS2) connected to its inputs. Switch (S50) connects the inverting input of amplifier (A1) to its output, and switch (S40) connects the non-inverting input of (A1) to a voltage reference (VREF) matching (VREF) applied to (AMP2). Switches (S30) and (S35) connect (CS1) and (CS2) to the demultiplexer input (2).