Abstract: An amplifier is configured to provide both common-mode and differential-mode compensation to ensure stability in telecommunications circuits or other circuits where both common mode and differential mode signal paths are provided. The amplifier includes two interconnected operational amplifiers AMPA and AMPB. Common mode compensation is provided by connecting one or more capacitors with a total value CCOMMON connected from a gain node at the input of an inverter in one of the amplifiers AMPA or AMPB to the output of the inverter in the other amplifier. Differential mode compensation can be provided by connecting a capacitor with value CCOMP at the gain node of each of the amplifiers AMPA or AMPB. Alternatively, both differential mode and Miller effect compensation can be provided by connecting one or more capacitors with total value CCOMP from the input to the output of components forming the inverter in each of the amplifiers AMPA and AMPB.

Abstract: A rail-to-rail operational amplifier to extract a true mean of two signals. The amplifier includes a first amplifier input stage adapted to operate when a mean of the two signals is near an upper rail voltage. A second amplifier input stage is adapted to operate when the mean of the two signals is near a lower rail voltage. A transitioning circuit is adapted to control how much each of the first and the second amplifier input stages contributes to an input of a high-gain amplifier output stage. An output of the high-gain amplifier output stage is fed back to both the n-type amplifier input stage and the p-type amplifier input stage via a matched buffer stage.

Abstract: A method and apparatus for generating reference voltages for a flat panel display system includes using a digital to analog converter (DAC) to supply multiple reference voltages to the flat panel display system, and wherein the DAC is adapted to accept digital input voltage reference from one of a plurality of registers and is adapted to provide an analog output to a demultiplexer, which includes a plurality of selectable sample and hold circuits.

Abstract: Double buffering of serial transfers is provided in order to allow for increased serial transfer rate without requiring increased internal processing speeds. A serial controller serially receives a word including address bits and data bits. During a write operation, the address bits are serially shifted into an address shift register, and the data bits are serially shifted into a data shift register. After the address bits and data bits are completely shifted into the respective address and data shift registers, the address bits and data bits are transferred in parallel to address and data holding registers. After the parallel transfers of the address bits and data bits from the address and data shift registers to the address and data holding registers, the address and data shift registers are available to serially receive additional address bits and data bits of an additional word.

Abstract: A rail-to-rail operational amplifier to extract a true mean of two signals. The amplifier includes a first amplifier input stage adapted to operate when a mean of the two signals is near an upper rail voltage. A second amplifier input stage is adapted to operate when the mean of the two signals is near a lower rail voltage. A transitioning circuit is adapted to control how much each of the first and the second amplifier input stages contributes to an input of a high-gain amplifier output stage. An output of the high-gain amplifier output stage is fed back to both the n-type amplifier input stage and the p-type amplifier input stage via a matched buffer stage.

Abstract: Methods and systems and apparatuses for reducing power consumption, in an environment including a laser driver that drives a laser diode, are provided. The voltage drop across a laser diode, driven by a laser driver, is monitored. This enables a supply voltage, used to power the laser driver, to be appropriately adjusted, based at least in part on the monitored voltage drop. For example, the supply voltage is increased when the monitored voltage drop across the laser diode increases, and decreased when the monitored voltage drop across the laser diode decreases.

Abstract: Optical pick-up units and laser drivers are disclosed, which can be used in various types of information recording/reproducing apparatuses, such as, but not limited to, DVD and CD drives, DVD camcorders, and DVD video recorders. A laser driver integrated circuit (LDIC) includes an automatic power controller, a running optical power controller, and a write strategy generator. The LDIC can be part of a chip-set, to be located on an optical pick-up unit (OPU). The chip-set can also include a power monitor integrated circuit (PMIC) to monitor the laser diode, and a photo-detector integrated circuit (PDIC) to detect light produced by the laser diode. The PMIC and the PDIC each include their own offset, gain and sample-and-hold circuitry.

Abstract: A laser driver includes a programmable damping resistor that provides an adjustable damping resistance to improve a laser light output response. The laser driver can also includes a controller that is adapted to adjust the programmable damping resistor based on an input signal. Such an input signal can, for example, specify characteristics of a driven load, components that make up the load, or the like. The controller can then determine and select a desirable damping resistance based on the provided input.

Abstract: A method and apparatus for generating reference voltages for a flat panel display system using a digital to analog converter (DAC) to supply multiple reference voltages to the flat panel display system. The DAC is adapted to accept digital input voltage reference from one of a plurality of registers and to provide an analog output to one of a plurality of sample and hold circuits. A controller selects which one of the plurality of registers is coupled to the DAC input, and selects which one of the plurality of sample and hold circuits is coupled to the DAC output.

Abstract: Improved systems and methods are provided for driving a column of display elements having a parasitic capacitance. Following a light emitting phase in a row time period, the column is partially discharged. During an initial phase within a next row time period, the column of display elements is pre-charged, if a light emitting phase is to be performed within the next row time period. Otherwise, the column of display elements is further discharged if a light emitting phase is not to be performed within the next row time period.

Abstract: Methods and system are provided for automatic power control of a laser diode, e.g., in a laser driver. In accordance with an embodiment of the present invention, a power controller includes a detector circuit adapted to detect the output of the laser diode and to produce a measured output therefrom. A comparator compares a desired output to the measured output, and produces an error signal therefrom. The error signal is provided to an integrator circuit that produces an integrated error signal. At least one digital-to-analog converter (DAC) uses the integrated error signal to produce a current drive signal that drives the laser diode.

Abstract: An improved relaxation oscillator circuit is provided using conventional CMOS device shunted with a current source (101 and 103) at each load of two cross-coupled gain stages. The improved oscillator uses a clamp voltage reference (134), to control the voltage swing across the charging/discharging capacitor (118). The improvements provide improved speed to power ratio, increased frequency tuning range, and less process and temperature variation effects. A transistor (130) and current source (138) replicate output transistors (110, 114) and current sources (101, 103). An amplifier (132) receives a clamp voltage reference (134) and current from the transistor (130) and current source (138) and functions to provide necessary drive currents to the gates of transistors (110, 114) which drive the outputs (VOR, VOL).

Abstract: An amplifier is configured to provide both common-mode and differential-mode compensation to ensure stability in telecommunications circuits or other circuits where both common mode and differential mode signal paths are provided. The amplifier includes two interconnected operational amplifiers AMPA and AMPB. Common mode compensation is provided by connecting one or more capacitors with a total value CCOMMON connected from a gain node at the input of an inverter in one of the amplifiers AMPA or AMPB to the output of the inverter in the other amplifier. Differential mode compensation can be provided by connecting a capacitor with value CCOMP at the gain node of each of the amplifiers AMPA or AMPB. Alternatively, both differential mode and Miller effect compensation can be provided by connecting one or more capacitors with total value CCOMP from the input to the output of components forming the inverter in each of the amplifiers AMPA and AMPB.

Abstract: A circuit for generating video synchronization timing signals includes a negative peak detector (FIG. 5) for following variations of a composite video signal (FIG. 1), rather than clamping the most negative voltage of the composite video signal. The negative peak detector provides a voltage level VTIP representative of the voltage at the synchronization tip of the composite video signal. A sample and hold circuit (700, 702, 704) is used to add an offset VSLICE to VTIP, VSLICE being a voltage level of the breezeway, color burst, or back porch segments of the composite video signal, or a combination of these segments. The sample and hold circuit generates a signal VREF, and is connected by a resistor divider (708,710) to the negative peak detector to form the signal VTIP+VSLICE provided to an amplifier (606) functioning as a comparator. The signal VSLICE+VTIP is compared in comparator (606) with the composite video signal to provide an overall circuit output.

Abstract: A silicon on insulator substrate is provided to include the following: a handle wafer; a layer of bonding material; a device wafer, the device wafer including at least one buried impurity region extending from the layer of bonding material upward into the device wafer; and an epitaxial silicon layer provided on a second surface of the device wafer. The silicon on insulator substrate with this configuration can be made with a minimal possible thickness.

Abstract: A circuit for generating video synchronization timing signals includes a negative peak detector (FIG. 5) for following variations of a composite video signal (FIG. 1), rather than clamping the most negative voltage of the composite video signal. The negative peak detector provides a voltage level VTIP representative of the voltage at the synchronization tip of the composite video signal. A sample and hold circuit (700, 702, 704) is used to add an offset VSLICE to VTIP, VSLICE being a voltage level of the breezeway, color burst, or back porch segments of the composite video signal, or a combination of these segments. The sample and hold circuit generates a signal VREF, and is connected by a resistor divider (708,710) to the negative peak detector to form the signal VTIP+VSLICE provided to an amplifier (606) functioning as a comparator. The signal VSLICE+VTIP is compared in comparator (606) with the composite video signal to provide an overall circuit output.

Abstract: An improved class-G amplifier (FIG. 2) is provided by adding a first capacitor (82) between the input of current mirror (18) and node p, and by adding a second capacitor (84) between the input of current mirror (20) and node m. The added capacitors (82) and (84) can be sized to stabilize frequency responses when high power supplies are enabled. The added capacitors (82) and (84) further function to reduce transient currents during switching through the crossover points between first upper and lower power supplies (Vsp1, Vsph) and between second upper and lower power supplies (Vsm1, Vsmh).

Abstract: The disclosure describes a current feedback amplifier that contains an additional pair of emitter follower transistors connected between inputs of current mirrors, with a capacitor connected to the common emitters of the emitter follower transistors to reduce discontinuities in the output current provided from the current mirrors. The capacitor is used to turn on the non-dominant current mirror prior to the time it is required to dominate the output. In this manner, glitches introduced due to delays in a current mirror switching from an off state to an on state are significantly reduced.

Abstract: A delay circuit is provided for use in a ring oscillator of a phase locked loop (PLL). The delay circuit includes a differential pair of NMOS transistors 102 and 103 with an NMOS transistor 101 providing the tail current for the differential pair. Complementary NMOS and PMOS load transistors 104,106 and 105, 107 provide loads for the differential transistor 102 and 103. Transistors 111-114 and 121-122 together with an amplifier 130 provide biasing for the delay device. The amplifier 130 has a non-inverting input set to VDD−VCLAMP. As configured, a constant output voltage swing from VDD to VDD−VCLAMP is provided at the outputs VOUT+ and VOUT− of the delay device, independent of a control voltage VCTL used to set the tail current. The NMOS load transistor 104, as opposed to the PMOS transistor 4 in FIG. 1, does not contribute to the gate parasitic capacitance enabling a high operation speed without consumption of more supply current.

Abstract: An improved amplifier includes an input stage differential amplifier (100) with an output forming a gain node (102), an output stage buffer (104) having an input connected to the gain node (102), a compensation capacitor (106) connected from the gain node (102) to ground, and a correction amplifier (200) with a first input connected to the output of the output stage buffer (104), a second input connected to the input of the output stage buffer (104), and having an output connected to the gain node (102), the correction amplifier further including a correction capacitor (304) connected between the input and output of the output stage buffer (104). The correction capacitor (304) preferably has a capacitance value (C′) set equal to the capacitance (Ccomp) of the compensation capacitor (106).