Abstract: A method and system for use with VLIW processing architectures for avoiding redundant speculative computations in the compilation of the innermost loops. The method includes identifying a plurality of compiled flow paths, where each of the paths includes a plurality of conditions associated with the loop that permits transformation of the loop for more optimum execution. It is then determined whether the loop has an inductive variable and a conditional statement that depends on the inductive variable. It is also determined whether the loop set up values of the inductive variables to subsets, and at least one of which the conditional statement is a loop invariant. Finally, if conditions in the determination steps satisfy the conditions of one of the paths, the loop is transformed into two consecutive loops executable with a reduced set of values of the inductive variable.

Abstract: A fully static level translation circuit having a standby power close to zero. The level translation circuit for translating the voltage level of an input signal having a first voltage level to form an output signal having a second voltage level. The translation circuit comprises an input stage having logic to receive the input signal having the first voltage level and to create a first stage output signal, an output stage having logic to receive the first stage output signal and produce the output signal having the second voltage level, and a reset stage having logic to receive the first stage output signal and the output signal and to produce a reset stage output signal that is coupled to the output stage.

Abstract: The present invention decreases the delay associated with loading an array from memory by employing an asynchronous array preload unit. The asynchronous array preload unit provides continuous preliminary loading of data arrays located in a memory subsystem into a prefetch buffer. Array loading is performed asynchronously with respect to execution of the main program.