Patents Assigned to Elm Technology Corporation
  • Patent number: 8933715
    Abstract: The Configurable Vertical Integration [CVI] invention pertains to methods and apparatus for the enhancement of yields of 3D or stacked integrated circuits and herein referred to as a CVI Integrated Circuit [CVI IC]. The CVI methods require no testing of circuit layer components prior to their fabrication as part of a 3D integrated circuit. The CVI invention uses active circuitry to configure the CVI IC as a means to isolate or prevent the use of defective circuitry. CVI circuit configuration method can be predominately described as a large grain method.
    Type: Grant
    Filed: March 13, 2013
    Date of Patent: January 13, 2015
    Assignee: Elm Technology Corporation
    Inventor: Glenn J. Leedy
  • Patent number: 8080442
    Abstract: The Vertical System Integration (VSI) invention herein is a method for integration of disparate electronic, optical and MEMS technologies into a single integrated circuit die or component and wherein the individual device layers used in the VSI fabrication processes are preferably previously fabricated components intended for generic multiple application use and not necessarily limited in its use to a specific application. The VSI method of integration lowers the cost difference between lower volume custom electronic products and high volume generic use electronic products by eliminating or reducing circuit design, layout, tooling and fabrication costs.
    Type: Grant
    Filed: June 21, 2008
    Date of Patent: December 20, 2011
    Assignee: Elm Technology Corporation
    Inventor: Glenn J Leedy
  • Patent number: 8035233
    Abstract: A Three-Dimensional Structure (3DS) Memory allows for physical separation of the memory circuits and the control logic circuit onto different layers such that each layer may be separately optimized. One control logic circuit suffices for several memory circuits, reducing cost Fabrication of 3DS memory involves thinning of the memory circuit to less than 50 ?m in thickness and bonding the circuit to a circuit stack while still in wafer substrate form. Fine-grain high density inter-layer vertical bus connections are used. The 3DS memory manufacturing method enables several performance and physical size efficiencies, and is implemented with established semiconductor processing techniques.
    Type: Grant
    Filed: March 3, 2003
    Date of Patent: October 11, 2011
    Assignee: Elm Technology Corporation
    Inventor: Glenn J Leedy
  • Patent number: 7705466
    Abstract: A Three-Dimensional Structure (3DS) Memory allows for physical separation of the memory circuits and the control logic circuit onto different layers such that each layer may be separately optimized. One control logic circuit suffices for several memory circuits, reducing cost. Fabrication of 3DS memory involves thinning of the memory circuit to less than 50 ?m in thickness and bonding the circuit to a circuit stack while still in wafer substrate form. Fine-grain high density inter-layer vertical bus connections are used. The 3DS memory manufacturing method enables several performance and physical size efficiencies, and is implemented with established semiconductor processing techniques.
    Type: Grant
    Filed: September 26, 2003
    Date of Patent: April 27, 2010
    Assignee: Elm Technology Corporation
    Inventor: Glenn J Leedy
  • Patent number: 7550805
    Abstract: General purpose methods for the fabrication of integrated circuits from flexible membranes formed of very thin low stress dielectric materials, such as silicon dioxide or silicon nitride, and semiconductor layers. Semiconductor devices are formed in a semiconductor layer of the membrane. The semiconductor membrane layer is initially formed from a substrate of standard thickness, and all but a thin surface layer of the substrate is then etched or polished away. In another version, the flexible membrane is used as support and electrical interconnect for conventional integrated circuit die bonded thereto, with the interconnect formed in multiple layers in the membrane. Multiple die can be connected to one such membrane, which is then packaged as a multi-chip module. Other applications are based on (circuit) membrane processing for bipolar and MOSFET transistor fabrication, low impedance conductor interconnecting fabrication, flat panel displays, maskless (direct write) lithography, and 3D IC fabrication.
    Type: Grant
    Filed: June 11, 2003
    Date of Patent: June 23, 2009
    Assignee: ELM Technology Corporation
    Inventor: Glenn Joseph Leedy
  • Patent number: 7504732
    Abstract: A Three-Dimensional Structure (3DS) Memory allows for physical separation of the memory circuits and the control logic circuit onto different layers such that each layer may be separately optimized. One control logic circuit suffices for several memory circuits, reducing cost. Fabrication of 3DS memory involves thinning of the memory circuit to less than 50 ?m in thickness and bonding the circuit to a circuit stack while still in wafer substrate form. Fine-grain high density interlayer vertical bus connections are used. The 3DS memory manufacturing method enables several performance and physical size efficiencies, and is implemented with established semiconductor processing techniques.
    Type: Grant
    Filed: August 19, 2002
    Date of Patent: March 17, 2009
    Assignee: Elm Technology Corporation
    Inventor: Glenn J. Leedy
  • Patent number: 7485571
    Abstract: General purpose methods for the fabrication of integrated circuits from flexible membranes formed of very thin low stress dielectric materials, such as silicon dioxide or silicon nitride, and semiconductor layers. Semiconductor devices are formed in a semiconductor layer of the membrane. The semiconductor membrane layer is initially formed from a substrate of standard thickness, and all but a thin surface layer of the substrate is then etched or polished away. In another version, the flexible membrane is used as support and electrical interconnect for conventional integrated circuit die bonded thereto, with the interconnect formed in multiple layers in the membrane. Multiple die can be connected to one such membrane, which is then packaged as a multi-chip module. Other applications are based on (circuit) membrane processing for bipolar and MOSFET transistor fabrication, low impedance conductor interconnecting fabrication, flat panel displays, maskless (direct write) lithography, and 3D IC fabrication.
    Type: Grant
    Filed: September 19, 2003
    Date of Patent: February 3, 2009
    Assignee: Elm Technology Corporation
    Inventor: Glenn J Leedy
  • Patent number: 7479694
    Abstract: General purpose methods for the fabrication of integrated circuits from flexible membranes formed of very thin low stress dielectric materials, such as silicon dioxide or silicon nitride, and semiconductor layers. Semiconductor devices are formed in a semiconductor layer of the membrane. The semiconductor membrane layer is initially formed from a substrate of standard thickness, and all but a thin surface layer of the substrate is then etched or polished away. In another version, the flexible membrane is used as support and electrical interconnect for conventional integrated circuit die bonded thereto, with the interconnect formed in multiple layers in the membrane. Multiple die can be connected to one such membrane, which is then packaged as a multi-chip module. Other applications are based on (circuit) membrane processing for bipolar and MOSFET transistor fabrication, low impedance conductor interconnecting fabrication, flat panel displays, maskless (direct write) lithography, and 3D IC fabrication.
    Type: Grant
    Filed: December 19, 2003
    Date of Patent: January 20, 2009
    Assignee: Elm Technology Corporation
    Inventor: Glenn J Leedy
  • Patent number: 7474004
    Abstract: A Three-Dimensional Structure (3DS) Memory allows for physical separation of the memory circuits and the control logic circuit onto different layers such that each layer may be separately optimized. One control logic circuit suffices for several memory circuits, reducing cost. Fabrication of 3DS memory involves thinning of the memory circuit to less than 50 ?m in thickness and bonding the circuit to a circuit stack while still in wafer substrate form. Fine-grain high density inter-layer vertical bus connections are used. The 3DS memory manufacturing method enables several performance and physical size efficiencies, and is implemented with established semiconductor processing techniques.
    Type: Grant
    Filed: December 18, 2003
    Date of Patent: January 6, 2009
    Assignee: Elm Technology Corporation
    Inventor: Glenn J Leedy
  • Publication number: 20080302559
    Abstract: General purpose methods for the fabrication of integrated circuits from flexible membranes formed of very thin low stress dielectric materials, such as silicon dioxide or silicon nitride, and semiconductor layers. Semiconductor devices are formed in a semiconductor layer of the membrane. The semiconductor membrane layer is initially formed from a substrate of standard thickness, and all but a thin surface layer of the substrate is then etched or polished away. In another version, the flexible membrane is used as support and electrical interconnect for conventional integrated circuit die bonded thereto, with the interconnect formed in multiple layers in the membrane. Multiple die can be connected to one such membrane, which is then packaged as a multi-chip module. Other applications are based on (circuit) membrane processing for bipolar and MOSFET transistor fabrication, low impedance conductor interconnecting fabrication, flat panel displays, maskless (direct write) lithography, and 3D IC fabrication.
    Type: Application
    Filed: January 18, 2008
    Publication date: December 11, 2008
    Applicant: Elm Technology Corporation
    Inventor: Glenn Joseph Leedy
  • Publication number: 20080284611
    Abstract: The Vertical System Integration (VSI) invention herein is a method for integration of disparate electronic, optical and MEMS technologies into a single integrated circuit die or component and wherein the individual device layers used in the VSI fabrication processes are preferably previously fabricated components intended for generic multiple application use and not necessarily limited in its use to a specific application. The VSI method of integration lowers the cost difference between lower volume custom electronic products and high volume generic use electronic products by eliminating or reducing circuit design, layout, tooling and fabrication costs.
    Type: Application
    Filed: June 21, 2008
    Publication date: November 20, 2008
    Applicant: ELM TECHNOLOGY CORPORATION
    Inventor: Glenn J. Leedy
  • Publication number: 20080254572
    Abstract: The Vertical System Integration (VSI) invention herein is a method for integration of disparate electronic, optical and MEMS technologies into a single integrated circuit die or component and wherein the individual device layers used in the VSI fabrication processes are preferably previously fabricated components intended for generic multiple application use and not necessarily limited in its use to a specific application. The VSI method of integration lowers the cost difference between lower volume custom electronic products and high volume generic use electronic products by eliminating or reducing circuit design, layout, tooling and fabrication costs.
    Type: Application
    Filed: June 21, 2008
    Publication date: October 16, 2008
    Applicant: ELM TECHNOLOGY CORPORATION
    Inventor: Glenn J. Leedy
  • Publication number: 20080251941
    Abstract: The Vertical System Integration (VSI) invention herein is a method for integration of disparate electronic, optical and MEMS technologies into a single integrated circuit die or component and wherein the individual device layers used in the VSI fabrication processes are preferably previously fabricated components intended for generic multiple application use and not necessarily limited in its use to a specific application. The VSI method of integration lowers the cost difference between lower volume custom electronic products and high volume generic use electronic products by eliminating or reducing circuit design, layout, tooling and fabrication costs.
    Type: Application
    Filed: June 21, 2008
    Publication date: October 16, 2008
    Applicant: ELM TECHNOLOGY CORPORATION
    Inventor: Glenn J. Leedy
  • Publication number: 20080237591
    Abstract: The Vertical System Integration (VSI) invention herein is a method for integration of disparate electronic, optical and MEMS technologies into a single integrated circuit die or component and wherein the individual device layers used in the VSI fabrication processes are preferably previously fabricated components intended for generic multiple application use and not necessarily limited in its use to a specific application. The VSI method of integration lowers the cost difference between lower volume custom electronic products and high volume generic use electronic products by eliminating or reducing circuit design, layout, tooling and fabrication costs.
    Type: Application
    Filed: May 9, 2008
    Publication date: October 2, 2008
    Applicant: Elm Technology Corporation
    Inventor: Glenn J. Leedy
  • Patent number: 7402897
    Abstract: The Vertical System Integration (VSI) invention herein is a method for integration of disparate electronic, optical and MEMS technologies into a single integrated circuit die or component and wherein the individual device layers used in the VSI fabrication processes are preferably previously fabricated components intended for generic multiple application use and not necessarily limited in its use to a specific application. The VSI method of integration lowers the cost difference between lower volume custom electronic products and high volume generic use electronic products by eliminating or reducing circuit design, layout, tooling and fabrication costs.
    Type: Grant
    Filed: August 8, 2003
    Date of Patent: July 22, 2008
    Assignee: Elm Technology Corporation
    Inventor: Glenn J. Leedy
  • Patent number: 7385835
    Abstract: General purpose methods for the fabrication of 5 integrated circuits from flexible membranes formed of very thin low stress dielectric materials, such as silicon dioxide or silicon nitride, and semiconductor layers. Semiconductor devices are formed in a semiconductor layer of the membrane. The semiconductor membrane layer is initially forced from a substrate of standard thickness, and all but a thin surface layer of the substrate is then etched or polished away. In another version, the flexible membrane is used as support and electrical interconnect for conventional integrated circuit die bonded thereto, with the interconnect formed in multiple layers in the membrane. Multiple die can be connected to one such membrane, which is then packaged as a multi-chip module. Other applications are based on (circuit) membrane processing for bipolar and MOSFET transistor fabrication, low impedance conductor interconnecting fabrication, flat panel displays, maskless (direct write) lithography, and 3D 1C fabrication.
    Type: Grant
    Filed: December 18, 2003
    Date of Patent: June 10, 2008
    Assignee: Elm Technology Corporation
    Inventor: Glenn J Leedy
  • Patent number: 7307020
    Abstract: General purpose methods for the fabrication of integrated circuits from flexible membranes formed of very thin low stress dielectric materials, such as silicon dioxide or silicon nitride, and semiconductor layers. Semiconductor devices are formed in a semiconductor layer of the membrane. The semiconductor membrane layer is initially formed from a substrate of standard thickness, and all but a thin surface layer of the substrate is then etched or polished away. In another version, the flexible membrane is used as support and electrical interconnect for conventional integrated circuit die bonded thereto, with the interconnect formed in multiple layers in the membrane. Multiple die can be connected to one such membrane, which is then packaged as a multi-chip module. Other applications are based on (circuit) membrane processing for bipolar and MOSFET transistor fabrication, low impedance conductor interconnecting fabrication, flat panel displays, maskless (direct write) lithography, and 3D IC fabrication.
    Type: Grant
    Filed: December 18, 2003
    Date of Patent: December 11, 2007
    Assignee: Elm Technology Corporation
    Inventor: Glenn J Leedy
  • Patent number: 7242012
    Abstract: General purpose methods for the fabrication of integrated circuits from flexible membranes formed of very thin low stress dielectric materials, such as silicon dioxide or silicon nitride, and semiconductor layers. Semiconductor devices are formed in a semiconductor layer of the membrane. The semiconductor membrane layer is initially formed from a substrate of standard thickness, and all but a thin surface layer of the substrate is then etched or polished away. In another version, the flexible membrane is used as support and electrical interconnect for conventional integrated circuit die bonded thereto, with the interconnect formed in multiple layers in the membrane. Multiple die can be connected to one such membrane, which is then packaged as a multi-chip module. Other applications are based on (circuit) membrane processing for bipolar and MOSFET transistor fabrication, low impedance conductor interconnecting fabrication, flat panel displays, maskless (direct write) lithography, and 3D IC fabrication.
    Type: Grant
    Filed: March 7, 2003
    Date of Patent: July 10, 2007
    Assignee: Elm Technology Corporation
    Inventor: Glenn J Leedy
  • Patent number: 7223696
    Abstract: General purpose methods for the fabrication of integrated circuits from flexible membranes formed of very thin low stress dielectric materials, such as silicon dioxide or silicon nitride, and semiconductor layers. Semiconductor devices are formed in a semiconductor layer of the membrane. The semiconductor membrane layer is initially formed from a substrate of standard thickness, and all but a thin surface layer of the substrate is then etched or polished away. In another version, the flexible membrane is used as support and electrical interconnect for conventional integrated circuit die bonded thereto, with the interconnect formed in multiple layers in the membrane. Multiple die can be connected to one such membrane, which is then packaged as a multi-chip module. Other applications are based on (circuit) membrane processing for bipolar and MOSFET transistor fabrication, low impedance conductor interconnecting fabrication, flat panel displays, maskless (direct write) lithography, and 3D IC fabrication.
    Type: Grant
    Filed: January 27, 2004
    Date of Patent: May 29, 2007
    Assignee: Elm Technology Corporation
    Inventor: Glenn J Leedy
  • Patent number: 7193239
    Abstract: A Three-Dimensional Structure (3DS) Memory allows for physical separation of the memory circuits and the control logic circuit onto different layers such that each layer may be separately optimized. One control logic circuit suffices for several memory circuits, reducing cost. Fabrication of 3DS memory involves thinning of the memory circuit to less than 50 ?m in thickness and bonding the circuit to a circuit stack while still in wafer substrate form. Fine-grain high density inter-layer vertical bus connections are used. The 3DS memory manufacturing method enables several performance and physical size efficiencies, and is implemented with established semiconductor processing techniques.
    Type: Grant
    Filed: July 3, 2003
    Date of Patent: March 20, 2007
    Assignee: Elm Technology Corporation
    Inventor: Glenn J Leedy